High speed multiplier using carry-save/propagate pipeline with s

Details High speed multiplier using carry-save/propagate pipeline with s High speed multiplier using carry-save/propagate pipeline with s

1979-05-04

1980-10-14

Malzahn, David H.

Boots, shoes, and leggings

364786, G06F 752, G06F 750

Patent

active

042285208

ABSTRACT:
A high speed multiply apparatus minimizes latch requirements and I/O pin requirement between chips by a new configuration which iteratively adds four multiples of a multiplicand in a stage of 4-2 carry save adders which then feed four-bit parallel adders each having four sum outputs and a carry output from the highest order bit position. Only the sum outputs are latched and then fed to a carry propagate adder on each iteration for addition to the previous partial products. Only the single carry output from each of the 4-bit parallel adders needs to be latched and then fed to another 4-bit parallel adder.

REFERENCES:
patent: 3515344 (1970-06-01), Goldschmidt et al.
patent: 3691359 (1972-09-01), Dell et al.
patent: 3840727 (1974-10-01), Amdahl et al.
patent: 4041292 (1977-08-01), Kindell
Larson "High-Speed Multiply Using Four Input Carry-Save Adder", IBM Tech. Disclosure Bulletin, vol. 16, No. 7, Dec. 1973, pp. 2053-2054.

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