High speed multiplier

Boots – shoes – and leggings

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Details

3647462, G06F 752, G06F 738

Patent

active

051154080

ABSTRACT:
A multiplying circuit (10) receives a multiplicand A and multiplies it by multiplier B. An Octal recoder (18) recodes the multiplier B into octal digits having a value from 4 to -4. A tripling generator determines the product of three times the multipicand. Partial product generators (22a-h) connected to the Octal recoder multiplex between the multiplicand A and the 3*A product, and include shifter and inverter circuitry to generate the partial products. Signed digit adders (24a-d, 26a-b and 28) add the partial products.

REFERENCES:
patent: 4498177 (1985-02-01), Larson
patent: 4628472 (1986-12-01), Fensch
patent: 4718031 (1988-01-01), Nukiyama
patent: 4918639 (1990-04-01), Schwarz et al.
N. Takagi et al., "High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree", IEEE Trans. on Computers, vol. C-34, No. 9, Sep. 1985, pp. 789-796.
1987 IEEE International Conference on Computer Design: VLSI in Computers & Processors, IEEE Catalog No. 87CH2473-7, ISBN 0-8186-0802-1, ICCD '87 Oct. 5-Oct. 8, 1987.
IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr. 1985, Title: Improved Approach to the Use of Booth's Multiplication Algorithm.
Binary-Compatible Signed-Digit Arithmetic, Proceedings of the fall joint computer conference San Francisco, Oct. 1964, Baltimore enz. Spartan Books 1964, A.F.I.P.S. conference proceedings vol. 26 part. 1, 663/672, zie boekencat.

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