High speed multiplier

Details High speed multiplier High speed multiplier

1993-02-04

1993-10-12

Smith, Jerry

Boots, shoes, and leggings

364760, 364737, G06F 752, G06F 1100

Patent

active

052531953

ABSTRACT:
A high speed digital multiplier utilizes a variation in known shift-and-add algorithms. Each cycle, a single digit of the multiplier and the entire multiplicand are processed to form a "partial product" that is added to the result of the next cycle. The end result is a two part product, the high order product being generated by a carry-propagate adder, and the low order product being generated by a "spill adder" that produces one digit each cycle. Inputs of a carry-propagate adder are fed directly from outputs of a carry-save adder rather than running sum and carry registers. With a multiplier digit of 16-bits, a fixed point halfword multiply requires one execution cycle, a fixed point fullword multiply requires two execution cycles, and a floating point long multiply requires four execution cycles with additional overhead if pre- or post-normalization is required.

REFERENCES:
patent: 3761698 (1973-09-01), Stephenson
patent: 3873820 (1975-03-01), Parr et al.
patent: 4594679 (1986-06-01), George et al.
patent: 4769780 (1988-09-01), Chang
patent: 4799183 (1989-01-01), Nakano et al.
patent: 4858163 (1989-08-01), Boreland
patent: 4989168 (1991-01-01), Kuroka et al.
IBM Technical Disclosure Bulletin, vol. 33, No. 6B, Nov. 1990, "High Speed Multiply Using a 5-Way Adder", K. Maass et al., pp. 315-317.
IBM TDB, vol. 20, No. 9, Feb. 1978, "Multiplier Decoding with Look-Ahead", A. Weinberger, pp. 3591-3593.

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