High-speed multiplexer circuit

Details High-speed multiplexer circuit High-speed multiplexer circuit

1987-10-16

1988-12-06

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

328104, H04J 302

Patent

active

047899840

ABSTRACT:
A high data rate multiplexer (MUX) architecture includes front-end and rear-end MUXs clocked at a system clock rate equal to one-half of the MUX output data rate. The front-end MUX selects inputs under control of select signals derived from multiple phases of a select clock. The select clock is derived from the system clock. The number of select signals is equal to the multiplexing factor of the MUX.

REFERENCES:
patent: 4317198 (1982-02-01), Johnson
patent: 4593390 (1986-06-01), Hildebrand et al.
R. Reimann and H-M. Rein, "THPM 15:1: A Bipolar 4:1 Time Division Multiplexer IC Operating up to 5.5 Gb/s", 1986, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 20, 1986, pp. 186-187.
H-M. Rein and R. Reimann, "6 Gbit/s Multiplexer and Regenerating Demultiplexer ICs for Optical Transmission Systems Based on a Standard Bipolar Technology", Electronics Letters, vol. 22, No. 19, Sep. 11, 1986; pp. 988-990.
K. C. Wang et al., "High-Speed Circuits for Lightwave Communication Systems Implemented with (AlGa)As/GaAs Heterojunction Bipolar Transistors", IEEE 1987 BCTM, Sep. 21, 1987, pp. 142-145.

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