High speed multiplexer

Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Converging with plural inputs and single output

Reexamination Certificate

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Reexamination Certificate

active

08085082

ABSTRACT:
According to one embodiment, a high speed multiplexer includes a number of data inputs, a number of hot code select inputs, and a final data output. In one embodiment, the high speed multiplexer utilizes a number of intermediate multiplexers, each receiving respective hot code select inputs and providing an intermediate data output. In one embodiment, each intermediate multiplexer has a critical delay path comprising a first NAND gate and a second NAND gate. In one implementation a four-to-one intermediate multiplexer comprises a first two-input NAND gate and a second four-input NAND gate. In one embodiment, a 32-to-1 high speed multiplexer comprises four four-to-one intermediate multiplexers. According to one implementation of this embodiment, the 32-to-1 multiplexer has a critical delay path from any of the data inputs to the final data output comprising a first NAND gate, a second NAND gate, a NOR gate, and a third NAND gate.

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patent: 2005/0256996 (2005-11-01), Watanabe
patent: 2007/0260856 (2007-11-01), Tran et al.

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