Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Converging with plural inputs and single output
Reexamination Certificate
1998-10-29
2001-05-29
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Converging with plural inputs and single output
C327S408000
Reexamination Certificate
active
06239646
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to multiplexers generally and, more particularly, to a high-speed, multiple-input multiplexer scheme.
BACKGROUND OF THE INVENTION
Multiplexers are logic devices that select between two or more inputs to be transferred to an output. It is desirable to have a multiplexer implemented with a symmetrical structure to minimize the skew when selecting between the various inputs. It is also desirable to minimize the delay introduced through the multiplexer. Additionally, it is often desirable to have a multiplexer with multiple number of inputs, in particular more than two inputs, and sometimes an odd number of inputs, while using a minimum number of components.
Referring to
FIG. 1
a,
a circuit
10
illustrating a four input multiplexer is shown. The multiplexer
10
has an input
12
, an input
14
, an input
16
, an input
18
and an output
20
. The input
12
receives a signal A, the input
14
receives a signal B, the input
16
receives a signal C and the input
18
receives a signal D. The output
20
presents a signal OUT. The multiplexer
10
also comprises an input
22
and an input
24
that receive a select signal SEL
0
and SEL
1
, respectively. The multiplexer
10
presents one of the signals A, B, C or D at the output
20
in response to the select signals SEL
0
and SEL
1
.
The multiplexer
10
, while performing the function of a four input multiplexer, actually comprises a number of two input multiplexers
26
a
-
26
n.
The multiplexer
26
a
receives the signal A and the signal B and presents an output to a first input of the multiplexer
26
n.
The multiplexer
26
b
receives the signal C and the signal D and presents a signal to a second input of the multiplexer
26
n.
The multiplexer
26
n
then presents either the signal received at the first or the second input as the signal OUT. The signal SEL
0
selects between the input A and B or the input C and D and the select signal SEL
1
selects between the signals received by the multiplexer
26
n
at the first or second inputs. Using the circuit
10
to implement a multiplexer with more than four inputs, additional number of stages must be implemented. The additional stages create additional delay through the multiplexer
10
which may result in higher skew. Additionally, if the number of inputs is not equal to 2
N
, circuitry may be wasted.
Referring to
FIG. 1
b,
a basic CML two-input multiplexer
40
is shown. A transistor Q
1
receives an input A_P, a transistor Q
2
receives an input A_N, a transistor Q
3
receives a signal B_P and a transistor Q
4
receives a signal B_N. The input A_P and A_N may be a differential input and the input B_P and B_N may be a differential input. The multiplexer
40
also comprises a resistor
42
, a resistor
44
, and a current source
46
. The multiplexer
40
represents one of the multiplexers
26
a
-
26
n.
Referring to
FIG. 2
, a multiplexer
50
is shown implemented using a second conventional approach. The multiplexer
50
comprises a number of transistor pairs
52
a
-
52
n
that each have a differential input (i.e., A_P and A_N; B_P and B_N; C_P and C_N; and D_P and D_N, respectively) and each have a corresponding select transistor
54
a
-
54
n.
The multiplexer
50
also comprises a current source
58
, a resistor
60
and a resistor
62
. The select transistors
54
a
and
54
b
are connected to a second stage select transistor
56
a.
The select transistors
54
c
and
54
n
are connected to a second stage select transistor
56
n.
The second stage select transistors
56
a
and
56
n
are connected to a current source
58
. At the lowest level, there is one differential pair (i.e.,
56
a
and
56
n
) controlled by a pair of select lines (i.e., SEL
0
_P and SEL
0
_N). The transistors
54
a
-
54
n
are stacked on top of the transistors
56
a
and
56
n
and contain two differential pairs (i.e.,
54
a
and
54
b,
and
54
c
and
54
n,
respectively) . The transistors
54
a
-
54
n
are controlled by a second pair of select lines (i.e., SEL
1
_P and SEL
1
_N). The top level contains the four differential pairs (
52
a
-
52
n
). The multiplexing operation is performed by the two lower levels (i.e., the transistors
54
a
-
54
n
and
56
a
-
56
n
). The circuit
50
has the disadvantages of (i) requiring multiple levels of select lines, (ii) requiring additional levels of cascading to implement more than four inputs, (iii) introducing a delay to the multiplexer due to the cascading, and (iv) increasing the internal delay, which results in higher skew. Additionally, redundant circuitry is implemented if the number of inputs is not equal to 2
N
.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a plurality of input devices, a plurality of select devices and a selector device. The plurality of inputs may each be configured to receive an input. The plurality of select devices may each be configured to present an output in response (i) one of said plurality of inputs and (ii) one of a plurality of select signals. The selector device may be configured to present the plurality of select signals, where only one of the select signals is active at a time.
The objects, features and advantages of the present invention include providing a multiplexer that (i) employs a single stage of multiplexing to minimize the delay and supply voltage requirements associated with each stage, (ii) provides a low skew operation due to symmetrical delay and symmetrical structures, (iii) does not provide unnecessary redundant components for arbitrary (i.e., odd or non-power of 2) numbers of inputs, (iv) eliminates the need for multi-level select lines, and (v) may be implemented using either CMOS or CML technology.
REFERENCES:
patent: 5731725 (1998-03-01), Rothenberger et al.
patent: 5982220 (1999-11-01), Kim
patent: 0314034 (1988-10-01), None
Dalmia Kamal
Navabi Mohammad J.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Nguyen Linh
Tran Toan
LandOfFree
High-speed, multiple-input multiplexer scheme does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High-speed, multiple-input multiplexer scheme, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-speed, multiple-input multiplexer scheme will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2532219