High-speed multi-port FIFO buffer circuit

Details High-speed multi-port FIFO buffer circuit High-speed multi-port FIFO buffer circuit

1991-10-21

1993-06-29

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 941, 36518901, 36518905, 365220, 36523001, 36523003, 36523008, H04L 1256

Patent

active

052240932

ABSTRACT:
A buffer memory for use in the output queue of a packet switching network is described. The buffer consists of two separate memories (160, 170, 260, 270) connected through a multiplexer (310) to the output of the switch. A memory access control (120, 220) processes the incoming data which arrives on only some of the input lines (130, 230) and outputs it on adjacent output lines (140, 150, 240, 250). The data is written concurrently into consecutive memory locations in one of the two memories (160, 170, 260, 270).

REFERENCES:
patent: 5016248 (1991-05-01), Kudoh
patent: 5046051 (1991-09-01), Doornhein et al.
IBM Technical Disclosure Bulletin, vol. 17, No. 3, Aug. 1974, pp. 933-934, New York, T. A. Williams, "High-speed Random-access Memory with Simultaneous Read/write Operation".
IBM Technical Disclosure Bulletin, vol. 32, No. 10B, Mar. 1990, pp. 176-177, New York, "Packet Switching Module".

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