High speed multi-modulus prescalar divider

Pulse or digital communications – Receivers – Angle modulation

Reexamination Certificate

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Details

C375S219000, C375S221000, C375S294000, C375S302000, C375S376000, C455S067130, C455S276100, C331S002000, C331S016000

Reexamination Certificate

active

07826563

ABSTRACT:
A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0.75, 0.875, 1, 1.125, or 1.25.

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patent: 7467317 (2008-12-01), Matsui
patent: 7647026 (2010-01-01), Darabi
patent: 2004/0232995 (2004-11-01), Thomsen et al.
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patent: 2007/0233903 (2007-10-01), Pyeon
patent: 2008/0024240 (2008-01-01), Wang
patent: 2008/0164917 (2008-07-01), Floyd et al.

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