High-speed multi-mode receiver

Details High-speed multi-mode receiver High-speed multi-mode receiver

2008-07-14

2010-02-09

Torres, Juan A (Department: 2611)

Pulse or digital communications

Testing

Phase error or phase jitter

C375S345000, C375S229000, C375S232000, C375S233000

Reexamination Certificate

active

07660350

ABSTRACT:
A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the information to the transmitter. The receiver is further operable to perform adaptive equalization to receive the signal transmitted by the transmitter.

REFERENCES:
patent: 5068873 (1991-11-01), Murakami
patent: 5881108 (1999-03-01), Herzberg et al.
patent: 6101312 (2000-08-01), Funayama
patent: 6243425 (2001-06-01), Langberg et al.
patent: 6400761 (2002-06-01), Smee et al.
patent: 6798828 (2004-09-01), Phanse
patent: 6891357 (2005-05-01), Camara et al.
patent: 6937054 (2005-08-01), Hsu et al.
patent: 7145413 (2006-12-01), Hsu et al.
patent: 7295618 (2007-11-01), Hsu et al.
patent: 2002/0044598 (2002-04-01), Frenkel et al.
patent: 2002/0094055 (2002-07-01), Cranford, Jr. et al.
patent: 2002/0095541 (2002-07-01), Cranford, Jr. et al.
patent: 2002/0136343 (2002-09-01), Cranford, Jr. et al.
patent: 2003/0035495 (2003-02-01), Laamanen et al.
patent: 2004/0114670 (2004-06-01), Cranford, Jr. et al.
patent: 2004/0170244 (2004-09-01), Cranford, Jr. et al.
patent: 2004/0207379 (2004-10-01), Camara et al.
patent: 2004/0239369 (2004-12-01), Hsu et al.
patent: 2004/0251983 (2004-12-01), Hsu et al.
patent: 2005/0040864 (2005-02-01), Ficken et al.
patent: 2005/0281343 (2005-12-01), Hsu et al.
patent: 2006/0159200 (2006-07-01), Hsu et al.
patent: 2007/0147559 (2007-06-01), Lapointe
Beukema “A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization”, IEEE Journal of Solid-State Circuits, vol. 40, Issue 12, Dec. 2005 pp. 2633-2645.
Fuji Yang et al., “CMOS Low-Power Multiple 2.5-3.125-Gb/s Serial Link Macrocell for High IO Bandwidth Network ICs”,IEEE Journal Of Solid-State Circuits, vol. 37, No. 12, Dec. 2002, pp. 1813-1821.
John Teifel et. al. “A High-Speed Clockless Serial Link Transceiver”,Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems, 2003.
Shyh-Jye Jou, et al. “Module Generator of Data Recovery for Serial Link Receiver”, National Central University, Taiwan, IEEE, 0-7803-8182-Mar. 2003.
Chih-Kong K. Yang et al. “A 0.8 μm CMOS 2.5 Gb/s Oversampled Receiver for Serial Links,”IEEE International Solid-State Circuits Conference, 1996.

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