High speed MOS RAM employing depletion loads

Details High speed MOS RAM employing depletion loads High speed MOS RAM employing depletion loads

1975-04-21

1976-03-23

Hecker, Stuart N.

Communications: electrical

Digital comparator systems

307238, G11C 706

Patent

active

039463699

ABSTRACT:
An MOS static random-access memory (RAM) in which high-speed is obtained, in part, through limiting the voltage swing on column lines. Column sense amplifiers are effectively de-coupled from a common read bus limiting capacitance associated with column lines. A unique address buffer assures that each address bit is generated simultaneously with its complement, thereby preventing multiple selections.

REFERENCES:
patent: 3848237 (1974-11-01), Geilhufe et al.
patent: 3868657 (1975-02-01), Hoffman et al.
patent: 3906463 (1975-09-01), Yu

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