High speed MOS circuits

Electrical transmission or interconnection systems – With nonswitching means responsive to external nonelectrical... – Temperature responsive

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307451, 307268, 307269, 307480, H03K 505, H03K 501, H03K 506, H03K 512

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active

047822538

ABSTRACT:
Integrated circuit chips with two (or more) multi-element logic paths--suffering from signal skew operation because of semiconductor processing variations--can be made to exhibit substantially reduced skew by designing the elements such that the sum of the pull-up delays in one logic path is approximately equal to the sum of the pull-up delays in the other logic path (or in each of the other logic paths) and such that the sum of all the delays (pull-down plus pull-up) in one path is substantially equal to the sum of all the delays in (each of) the other(s)--all in response to an input signal transition (low to high, high to low, or both) applied to each path.

REFERENCES:
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patent: 4104860 (1978-08-01), Stickel
patent: 4346343 (1982-08-01), Berndlmaier et al.
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patent: 4508983 (1985-02-01), Allgood et al.
patent: 4575646 (1986-03-01), Saneski
Gorajek, "Accurate Time-Delay from Two Inaccurate Circuits"; Electronic Engineering, pp. 20; 8/1978.
Dingwall, "Transistor Memory Precharge Circuit"; RCA Tech. Notes; TN No.: 1140; 2 pages, 2/18/76.
Farr, Jr., "Skew Compensation Circuit"; RCA Technical Notes; TN No.: 803; 11/15/1968, 3 pages.
Large Scale Integration Devices, Circuits, and Systems, M. J. Howes et al., (John Wiley & Sons, 1981), p. 120.

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