High speed module interconnection bus

Multiplex communications – Wide area network – Packet switching

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370 8511, H04J 312

Patent

active

049982443

ABSTRACT:
A method and apparatus for providing communication among N modules connected to a common communication bus uses a bus structure with a reserve line for signaling the occurrence of a reservation time slot during which time each of the N modules which have information to transmit may reserve a time for transmission over the bus. A plurality of at least N data lines are used for transmission of data words over the bus. Each of the N modules are also assigned use of one of the plurality of data lines for signaling during the reservation time slot that the module has information to transmit over the bus. The reserve line is also used for signaling, that a word of data being transmitted over the plurality of data lines is a last word in a current transmission to be transmitted by the module currently transmitting.

REFERENCES:
patent: 4451881 (1984-05-01), Grice et al.
patent: 4536873 (1985-08-01), Leete
patent: 4580261 (1986-04-01), Pelotte
patent: 4700341 (1987-10-01), Huang
patent: 4718061 (1988-01-01), Turner
Computer Networks, by Andrew Tanenbaum, 1981, Prentice-Hall, Inc., pp. 296-307.
IEEE Communications Magazine, Apr. 1988, vol. 26, No. 4, pp. 20-28, "The QPSX Man", by R. M. Newman et al.

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