High speed mis-type intergrated circuit with self-regulated back

Details High speed mis-type intergrated circuit with self-regulated back High speed mis-type intergrated circuit with self-regulated back

1994-11-14

1997-09-30

Nelms, David C.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327537, 327538, 327541, H01J 1982, G05F 110

Patent

active

056729952

ABSTRACT:
There are provided a MIS transistor having a substrate portion, a gate, a source, and a drain, a back-bias generator to be applied to the substrate portion of the MIS transistor, and a resistor interposed between the substrate portion of the MIS transistor and the back-bias generator so that the potential between the both ends thereof changes in a range from one value in the active mode to the other value in the standby mode of the MIS transistor. In the MIS transistor, the back bias is self-regulated so that it approaches to zero in the active mode, while it moves away from zero in the standby mode. Consequently, the threshold voltage is reduced in the active mode due to the back bias approaching to zero, so that higher-speed operation is performed. On the other hand, off-state leakage is suppressed in the standby mode due to the back bias moving away from zero. Thus, it becomes possible to constitute a semiconductor apparatus which operates at high speed with low power consumption.

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Tsukasa Ooishi et al., A Well-Synchronized Sensing/Equalizing Method For Sub-1.0v Operating Advaced DRAMs, pp. 81-82.

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