High-speed minimal logic self blank checking method for programm

Details High-speed minimal logic self blank checking method for programm High-speed minimal logic self blank checking method for programm

1995-03-03

1996-10-01

Nguyen, Tan T.

Static information storage and retrieval

Floating gate

Particular biasing

36518529, G11C 1602

Patent

active

055616313

ABSTRACT:
A programmable logic device (PLD) performs a self-test erase check operation on memory elements to verify if the PLD is completely erased. The output signals of the sense amplifiers associated with the PLD bitlines drive a plurality of NMOS devices. The NMOS devices share a common source (node), thereby providing in effect an n-input NOR gate, where n is the number of bitlines in the array. The memory cells associated with an entire wordline of the PLD memory array are simultaneously checked for an erased state by bringing the wordline under test high while keeping all other wordlines low. If all of the memory cells on a wordline are erased, every sense amplifier output is low, all of the NMOS devices are off, and the output signal of the NOR gate is high due to a weak pull-up on the common node, thereby indicating that the whole column is properly erased. If one or more memory cells on the selected wordline are not completely erased, then at least one sense amplifier output is high because the cell is not able to pull its bitline low to switch the sense amplifier. The high output of the sense amplifier turns on its associated NMOS device, thereby pulling down the voltage on the common node and providing a low output signal from the NOR gate, thereby indicating that additional erasing of the array is necessary.

REFERENCES:
patent: 4774421 (1988-09-01), Hartmann
patent: 5347490 (1994-09-01), Terada
patent: 5386388 (1995-01-01), Atwood
patent: 5400287 (1995-03-01), Fuchigami

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