Patent
1995-06-07
1998-01-13
Coleman, Eric
395800, G06F 710
Patent
active
057088004
ABSTRACT:
A microprocessor comprises a control section for receiving a transfer instruction and transferring N-bits of M-bit data stored at a transfer-source address in a first memory to a transfer-destination address in a second memory in response to a received transfer instruction. In this microprocessor, the transfer of N-bits is performed with the execution of a single transfer instruction. Hence, the memory area required for storing the transfer instructions is reduced, and the residual memory area can be used for other purposes, which improves the efficiency in the use of the memory. The control section stores in the first memory of the microprocessor all the interim results obtained during the execution of a transfer instruction and outputs only the final result to the external memory, reducing the number of machine cycles required for data transfer between the microprocessor and the memory, and further reducing the execution time for data transfer in the microprocessor.
REFERENCES:
patent: 4486848 (1984-12-01), Kaminski
patent: 4533992 (1985-08-01), Magar
patent: 4783837 (1988-11-01), Kawamura
patent: 5185859 (1993-02-01), Guttag
patent: 5459681 (1995-10-01), Harrison
patent: 5590350 (1996-12-01), Guttag
Nakamura Kazuo
Takahashi Hiroki
Tateishi Hiroshi
Coleman Eric
Mitsubishi Denki & Kabushiki Kaisha
Mitsubishi Electric Semiconductor Software Corporation
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