High speed memory with low standby current

Details High speed memory with low standby current High speed memory with low standby current

1995-03-07

1996-07-30

Nguyen, Tan T.

Static information storage and retrieval

Powering

365229, 365208, 365227, G11C 1140

Patent

active

055418856

ABSTRACT:
A semiconductor device, having an active operation mode wherein a large amount of current is consumed and a standby operation mode wherein a very small amount of current is consumed, comprises p-channel and n-channel MOS transistors, each having a source or drain as a connection node fixed to an "H" or "L" level in the standby operation mode. In the MOS transistors of the same channel, the threshold voltages V.sub.T1 and V.sub.T4 of transistors Q.sub.1 and Q.sub.4, which are cut off in the standby operation mode, are set to a level higher than the threshold voltages V.sub.T2 and V.sub.T3 of transistors Q.sub.2 and Q.sub.3, which are turned on in the standby operation mode (V.sub.T1 >V.sub.T2, .vertline.V.sub.T4 >V.sub.T3 .vertline.).

REFERENCES:
patent: 4983861 (1991-01-01), Kikuchi et al.
patent: 5124574 (1992-06-01), Ibaraki
patent: 5166902 (1992-11-01), Silver
patent: 5200921 (1993-04-01), Okajima
IEEE Journal of Solid-State circuits vol. 27, No. 5, Akinori Sekiyama, et al., "A 1-V Operating 256-kb Full-CMOS SRAM", May, 1992, pp. 776-782.

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