High speed memory with a multiplexed address bus

Details High speed memory with a multiplexed address bus High speed memory with a multiplexed address bus

1983-09-14

1986-06-17

Moffitt, James W.

Static information storage and retrieval

Addressing

Sync/clocking

365193, 365194, 364200, G11C 800, G11C 1140

Patent

active

045960046

ABSTRACT:
Memory access time, noise and costs are substantially reduced while reliability is increased by replacing fixed delay lines with a dynamic delay. This dynamic delay is placed on the same integrated circuit as the remainder of the memory access circuitry to eliminate tracking problems associated with off-chip delay lines. The dynamic delay element is activated after all of the row address strobe (RAS) bits have been generated. These RAS bits serve to strobe the row column address bits initially present on the address bus into the memory. After the delay time has elapsed an address multiplexor switches column address bits onto the address bus to replace the prior row address bits. As soon as this switch is completed column address strobe (CAS) bits are generated to strobe the column address bits into the memory.

REFERENCES:
patent: 3786277 (1974-01-01), Basse
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4060794 (1977-11-01), Feldman et al.
patent: 4293932 (1981-10-01), McAdams
patent: 4354259 (1982-10-01), Ishimoto
patent: 4412314 (1983-10-01), Proebsting
"1K CMOS RAM Needs Only 8 Pins", Electronic Product Design, Oct. 1981, p. 9.

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