High speed memory self-timing circuitry and methods for implemen

Details High speed memory self-timing circuitry and methods for implemen High speed memory self-timing circuitry and methods for implemen

1997-10-24

1999-12-07

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Sync/clocking

365210, 365194, 365 51, G11C 800

Patent

active

059994827

ABSTRACT:
A memory circuit that includes a memory core having an array of core cells is provided. The array of core cells are coupled to a plurality of wordlines and a plurality of bitline pairs. The memory circuit further includes a self-timing path that has a model core cell that is coupled to a model wordline, and the model wordline is driven by a model wordline driver. The self-timing path also includes a model sense amplifier that is coupled to the model core cell through a pair of model bitlines. The model wordline and the pair of model bitlines are each coupled to a plurality of dummy core cells to approximate an RC delay of a worst case core cell of the array of core cells. Further, the model wordline is a folded wordline, such that the model wordline has a termination at a location that is proximate to the model wordline driver.

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