Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-08-08
2001-07-03
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S063000
Reexamination Certificate
active
06256262
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a memory device, such as an SRAM, that has different read and write clock signals.
2. Description of the Related Art
Referring to
FIG. 1
, a conventional memory device is shown to comprise a global decoder circuit
11
, two pairs of memory cell arrays
12
each of which is disposed adjacent to a respective one of opposing first and second sides of the global decoder circuit
11
and is coupled to the global decoder circuit
11
, a write control circuit
13
coupled to and disposed adjacent to a third side of the global decoder circuit
11
between the first and second sides, a read control circuit
14
coupled to and disposed adjacent to a fourth side of the global decoder circuit
11
opposite to the third side, a pre-decoder circuit
15
coupled to the global decoder circuit
11
and the read control circuit
14
and disposed between the fourth side of the global decoder circuit
11
and the read control circuit
14
, a read clock buffer
16
disposed on one side of the read control circuit
14
opposite to the pre-decoder circuit
15
, a write clock buffer
17
disposed on one side of the read clock buffer
16
opposite to the read control circuit
14
, and a pair of data input buffers
18
, each of which is disposed at the third side of the global decoder circuit
11
adjacent to a respective one of the pairs of memory cell arrays
12
, and is coupled to an external data input device (not shown), the respective one of the pairs of memory cell arrays
12
and the write clock buffer
17
. The global decoder circuit
11
includes a write global decoder portion
111
and a read global decoder portion
112
. Each memory cell array
12
includes a local decoder portion
121
between two mxn cell array portions
122
. A multiplexer (MUX)
123
has an input side coupled to bit lines of the cell array portions
122
of the memory cell arrays
12
. A sense amplifier (SA)
124
is coupled to an output side of the multiplexer
123
. An output circuit (DO)
125
is coupled to an output end of the sense amplifier
124
, and is further coupled to the read clock buffer
16
.
A write operation for the aforesaid conventional memory device is conducted as follows: Input data to the memory cell arrays
12
are initially sent to the data input buffers
18
. When write address sets corresponding to the input data are received by the write control circuit
13
, the latter generates appropriate write address and write control signals that are provided to the write global decoder portion
111
of the global decoder circuit
11
to enable writing of the input data into the memory cell arrays
12
. At this time, the write global decoder portion
111
and the local decoder portions
121
of the memory cell arrays
12
decode the write address sets so that appropriate ones of the memory cells of the cell array portions
122
are activated. Write clock signals from the write clock buffer
17
are received by the data input buffers
18
so as to control the transmission of the input data from the data input buffers
18
to the memory cell arrays
12
. The input data are written into the activated ones of the memory cells of the cell array portions
122
at this stage.
A read operation for the aforesaid conventional memory device is conducted as follows: When read address sets are received by the read control circuit
14
, the latter generates appropriate read address and read control signals to the global decoder circuit
11
to enable reading of the memory cell arrays
12
. At this time, the pre-decoder circuit
15
, the read global decoder portion
112
and the local decoder portions
121
of the memory cell arrays
12
decode the read address sets so that appropriate ones of the memory cells of the cell array portions
122
are activated. Data in the activated ones of the memory cells of the cell array portions
122
are received by the multiplexer
123
. The output of the multiplexer
123
is sensed by the sense amplifier
124
, and is provided to the output circuit
125
. Read clock signals from the read clock buffer
16
are received by the output circuit
125
to control the transmission of output data to an external device (not shown).
Some of the drawbacks of the aforesaid conventional memory device are as follows:
1. Because the write clock buffer
17
and the data input buffers
18
are disposed on opposite sides of the global decoder circuit
11
, the distance between the write clock buffer
17
and the data input buffers
18
is relatively long such that parasitic effect is not negligible and can affect adversely synchronized transmission of the input data to the memory cell arrays
12
.
2. The signal strength at the bit lines of the cell array portions
122
is relatively weak, and is further weakened by coupling between the bit lines and the multiplexer
123
, thereby leading to errors in the data sensed by the sense amplifier
124
.
3. The memory cell arrays
12
are relatively large due to the presence of the local decoder portions
121
. The large memory cell arrays
12
require relatively long global word lines for connection to the global decoder circuit
11
. The relatively long global word lines are prone to errors due to parasitic effect.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a memory device of the aforesaid type that is capable of overcoming the above-mentioned drawbacks commonly associated with the prior art.
According to this invention, a memory device comprises a global decoder circuit, two memory cell array devices, two data input buffers, a write control circuit, write clock means, a read control circuit, two multiplexer sets, two output circuits, and read clock means.
The global decoder circuit has opposite first and second sides, and opposite third and fourth sides between the first and second sides.
Each of the memory cell array devices is disposed adjacent to a respective one of the first and second sides of the global decoder circuit, and has global word lines coupled to the global decoder circuit, and bit lines.
Each of the data input buffers is disposed at the third side of the global decoder circuit adjacent to a respective one of the memory cell arrays, is coupled to the respective one of the memory cell arrays, and is adapted to receive input data and to transmit the input data to the respective one of the memory cell arrays.
The write control circuit is coupled to and is disposed adjacent to the third side of the global decoder circuit. The write control circuit is adapted to receive write address sets corresponding to the input data and to generate appropriate write address and write control signals that are provided to the global decoder circuit upon receipt of the write address sets to enable writing of the input data into the memory cell array devices.
The write clock means, which is disposed adjacent to the third side of the global decoder circuit and which is coupled to the data input buffers, generates write clock signals that are provided to the data input buffers so as to control transmission of the input data from the data input buffers to the memory cell array devices.
The read control circuit is coupled to and is disposed adjacent to the fourth side of the global decoder circuit. The read control circuit is adapted to receive read address sets and to generate appropriate read address and read control signals that are provided to the global decoder circuit upon receipt of the read address sets to enable reading of the memory cell array devices.
Each of the multiplexer sets is coupled to the bit lines of a respective one of the memory cell array devices.
Each of the output circuits is coupled to a respective one of the multiplexer sets.
The read clock means, which is disposed adjacent to the fourth side of the global decoder circuit and which is coupled to the output circuits, generates read clock signals that are provided to the output circuits so as to control output of data by the output circuits.
The memory device further c
Chen Hsin-Kuang
Chen Hsing-Yi
Wang Jo-Yu
Wang Jyh-Ming
Le Vu A.
Phung Anh
Silicon Integrated Systems Corp.
Townsend and Townsend / and Crew LLP
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