High speed memory architecture

Details High speed memory architecture High speed memory architecture

2008-08-19

2010-12-07

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S222000, C365S164000, C365S194000, C365S051000, C365S063000

Reexamination Certificate

active

07848153

ABSTRACT:
Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.

REFERENCES:
patent: 5880987 (1999-03-01), Merritt
patent: 6237130 (2001-05-01), Soman et al.

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