High-speed memory and memory management system

Details High-speed memory and memory management system High-speed memory and memory management system

1982-07-02

1985-07-02

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 934

Patent

active

045272328

ABSTRACT:
A method and apparatus for accessing a particular location in a main memory of a computer in which virtual addresses from a CPU are separated into direct and indirect address segments. The direct address segment is applied directly to one of row and column control lines that identify such location in the memory and the indirect address segment is translated into a real address segment and applied to the other of the row and column control lines of the main memory that identify the particular memory location. The row and column control lines are strobed with sequential pulses such that the control line to which the direct address segment is applied is strobed prior to the control line to which the translated real address segment is applied.

REFERENCES:
patent: 3412382 (1968-11-01), Couleur et al.
patent: 3723976 (1973-03-01), Alvarez et al.
patent: 3902164 (1975-08-01), Kelley et al.

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