Boots – shoes – and leggings
Patent
1991-02-26
1993-12-28
Bowler, Alyssa H.
Boots, shoes, and leggings
364DIG1, 3649663, 3642517, 36523003, G06F 1200, G06F 1300
Patent
active
052747883
ABSTRACT:
A data processor which includes a central processing unit (CPU) coupled to an address bus for supplying an address to an external memory and a data bus for supplying data to the external memory and receiving data from the external memory, and a control logic for controlling data exchange between the CPU and the external memory with a predetermined unit amount of data processing of the central processing unit. The external memory includes first and second DRAMs and the CPU executes the data exchange with units of four words. Each DRAMs has a memory area divided into a number of sub-areas each have four continuous addresses, so that the sub-areas of the first DRAM and the sub-area of the second DRAM are alternately assigned in continuous addresses in one memory space formed of the first and second DRAMs. When an continuous addresses are supplied, a controller controls so that the first and second DRAMs are alternately accessed.
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patent: 4378594 (1983-03-01), Kenyon
patent: 4438512 (1984-03-01), Hartung et al.
patent: 4740911 (1988-04-01), Shar et al.
patent: 4918587 (1990-04-01), Pechter
patent: 5089993 (1992-02-01), Neal et al.
IBM Technical Disclosure Bulletin, vol. 22, No. 11, Split Cache with Variable Interleave Boundary, Apr. 1980 pp. 5183-5186.
Bowler Alyssa H.
NEC Corporation
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