High speed mask and logical combination operations for parallel

Details High speed mask and logical combination operations for parallel High speed mask and logical combination operations for parallel

1995-06-06

1997-07-29

An, Meng-Al T.

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395376, 36493141, 364933, 3649402, 3649405, 364229, 3642292, 3642293, 3642401, 3642444, 364247, 3642525, 364259, 3642591, 3642597, 364DIG1, G06F 1300, G06F 1516

Patent

active

056529074

ABSTRACT:
A computer system having a plurality of parallel processor units with each processor unit having an output bus of n bits and an associated mask register is provided. The computer system comprises a bus unit, coupled to the output bus of each processor unit and each associated mask register, for masking the output bus bits with bits in the mask register of each processor unit and logically combining the resulting masked bits from each processor unit into an output bus of n bits in one computer operation.

REFERENCES:
patent: 3980992 (1976-09-01), Levy et al.
patent: 4493053 (1985-01-01), Thompson
patent: 4933839 (1990-06-01), Kinoshita et al.
patent: 4992933 (1991-02-01), Taylor
patent: 5167029 (1992-11-01), Eikill et al.
patent: 5218713 (1993-06-01), Hammer et al.

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