High speed low skew clock circuit

Details High speed low skew clock circuit High speed low skew clock circuit

1990-02-13

1991-10-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 3072721, 307605, 307291, 307480, 328 63, H03K 500, H03K 329, H03K 513, H03K 700

Patent

active

050577018

ABSTRACT:
A clock buffer circuit achieves insensitivity to the particular voltage levels and drift therein of input signals used to generate the clock, by use of a differential common gate amplifier incorporating an internally generated threshold voltage. Four separate gain paths couple the differential common gate amplifier to an output stage. Two of the gain paths are used to propagate edges that cause respective abrupt transitions in each direction for a first of two complementary clock signals. The other two accomplish the same for the other complementary clock signal. Each gain path is optimized to propagate a leading edge of a particular direction (relative to its point of origin, the direction of the edge inverts as it goes from stage to stage). Of these four gain paths, a first pair are used to create a high level of drive for the low to high transitions in the clock signal and its complement. Because of the optimization, this drive cannot be removed as abruptly as it can be applied. A latch-like circuit in the gain paths cause early removal of the high level, or hard, drive, leaving in place a maintenance, or holding, level of drive. Each holding drive is abruptly removed by an associated gain path in the remaining pair of gain paths. The hard drive is left in place only long enough to ensure that the capacitance of the clock line is adequately charged. An anti-glitch mechanism bullet proofs the entire circuit against drive fights caused by ambiguities arising from slow transitions that might arise from the differential common gate amplifier.

REFERENCES:
patent: 4417158 (1983-11-01), Ito et al.
patent: 4837505 (1989-06-01), Mitsunobu

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