High speed, low power switched-capacitor digital-to-analog...

Details High speed, low power switched-capacitor digital-to-analog... High speed, low power switched-capacitor digital-to-analog...

2002-06-17

2003-09-16

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S144000

Reexamination Certificate

active

06621444

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to digital-to-analog converters, and more particularly to a switched capacitor digital-to-analog converter with selective precharging of a capacitor array.
2. Description of the Related Art
FIG. 1
shows a differential digital-to-analog converter (DAC) with two weighted capacitor arrays, indicated ArrayP and ArrayM, each formed of a predetermined number n of capacitors with capacitances varying according to a factor 2
i
, where i varies from 0 to n−1. Only four capacitors per array (C
0
p, C
1
p, C
2
p, Cip; C
0
m, C
1
m, C
2
m, Cim) are shown in the figure, with capacitances C,
2
C,
4
C,
2
i
C. Each capacitor of ArrayP has an electrode connected to a common node NSP and another electrode connected, through a corresponding switching arrangement SWPi to a first or a to a second reference voltage terminal, indicated by the respective voltages V
REFP
, V
REFM
, referred to a common reference node of the integrated circuit which embodies the DAC, such as the circuit ground.
Similarly, each capacitor of ArrayM has an electrode connected to a common node NSM and another electrode connected, through a corresponding switching arrangement SWMi, to the first or to the second reference voltage terminal V
REFP
, V
REFM.
The switching arrangements SWPi and SWMi operate like two-way switches controlled in phase opposition by a bit of a digital input code B(i) with i varying from 0 to n−1.
The voltage terminals V
REFP
and V
REFM
are output terminals of a circuit represented in this example as a buffer with single ended input and differential output. The input, indicated V
REF
, is connected to the output of a bias circuit (not shown) which provides a stable reference voltage V
REF
, substantially insensitive to variations of temperature, process and design parameters, and circuit power supply. The buffer is usually implemented as an integrated operational amplifier with a pass-band large enough to meet the converter requirements of switching speed and a current capability appropriate for the converter electric power requirements. As is known, the buffer contribution to the overall power consumption of the integrated circuit is large and in many cases is the largest portion of the converter power consumption.
When the converter capacitors are connected to V
REFP
or V
REFM
, the buffer outputs experience strong perturbations. This is because any change in the bit value of successive input digital codes requires a corresponding capacitor to be charged or discharged suddenly. Due to the limited frequency band, the operational amplifier cannot provide the necessary charges instantaneously and this causes spikes in the output reference voltages V
REFP
, V
REFM
. The higher the number of switched capacitors involved in the charge changing, the higher are the spikes. The nominal reference voltages are recovered in times depending on the slew rate and frequency band of the operational amplifier. FIG.
5
(
a
) shows a typical situation at the outputs of a prior art buffer:
VREFP
changes suddenly from 2.0 V to less than 1.2 V and
VREFM
changes from 0.5 V to about 1.2 V; the transient time is about 60 ns.
A prior art approach to mitigate the effect explained above, and thus increase the switching speed, is to design a buffer with higher power and band capabilities. This approach, however, implies difficult design problems, requires larger semiconductor areas for the buffer and bias circuitry and, above all, implies a higher power consumption.
BRIEF SUMMARY OF THE INVENTION
The disclosed embodiments of the present invention provide a switched capacitor digital-to-analog converter that can be operated at a high speed and has a low power consumption.
A switched capacitor digital-to-analog converter for providing analog output signals corresponding to input digital codes is provided that includes an input terminal and at least one output terminal, a first voltage generator for providing first and second reference voltages on first and second reference terminals, respectively, a second voltage generator for providing third and fourth reference voltages on third and fourth reference terminals, said third and fourth reference voltages being selected to match predetermined design values of the first and second reference voltages, respectively, at least one array of binary weighted capacitors, each capacitor having a first electrode connected to a common circuit node, which is connected to said at least one output terminal, and a second electrode selectively connected, through associated first switching means, to either one of the first and second reference terminals or, through associated second switching means, to either one of the third and fourth reference terminals means for monitoring the values of each bit of the input digital codes, control means coupled to the first and second switching means associated with each capacitor of the array to open or close selectively during a bit clock period the connections to the first, second, third and fourth terminals according to the following criterion:
when the monitoring means detects a bit value of the current input digital code B
j
to be equal to the corresponding bit value of the previous input digital code B
j−1
, the first switching means are enabled and the second switching means are disabled during the whole bit clock period,
when the monitoring means detects a bit value of a current input digital code B
j
to be different from the corresponding bit value of the previous input digital code B
j−1
, the first switching means are disabled and the second switching means are enabled during a starting time portion of the bit clock period, while the first switching means are enabled and the second switching means are disabled during the remaining portion of the bit clock period.


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patent: RE32313 (1986-12-01), Yamakido
patent: 5581252 (1996-12-01), Thomas
patent: 5684487 (1997-11-01), Timko
patent: 5952952 (1999-09-01), Choi et al.
patent: 6407689 (2002-06-01), Bazarjani et al.
patent: 6486812 (2002-11-01), Tanaka

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