Electrical pulse counters – pulse dividers – or shift registers: c – Shift register – Particular input circuit
Reexamination Certificate
2001-07-30
2002-12-03
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Shift register
Particular input circuit
C377S054000, C377S073000, C377S080000
Reexamination Certificate
active
06490332
ABSTRACT:
FIELD OF INVENTION
The present invention relates in general to high speed analog and digital circuits and in particular to high speed, low-power shift registers and circuits and methods using the same.
BACKGROUND OF INVENTION
One particular technique for performing analog to digital (A/D) conversion is through successive approximation. The basic successive approximation A/D converter (ADC) includes an analog comparator and a clocked feedback loop having a successive approximation register (SAR) and a digital to analog converter (DAC).
Generally, the analog input signal voltage is sampled onto an array of weighted capacitors, during the sampling phase, the top plates of which are coupled to one comparator input. The other comparator input is coupled to a comparison voltage, which could be a fixed reference voltage in a single-ended system or the voltage at the top plates of second capacitor array in a differential system.
During the first clock cycle of the subsequent conversion phase, the bottom plate of the capacitor representing the digital most significant bit (MSB) is coupled to a reference voltage while the bottom plates of the remaining capacitors in the array are coupled to ground or a second reference voltage (ground will be assumed here). The new top plate voltage appears at the input of the comparator and is compared against the comparison voltage. The new top plate voltage is a scaled version of
[
Voef
2
-
ain
]
·
k
where k is the ratio of capacitors. The sign of this quantity is the factor of interest. If the new top plate voltage is below the comparison voltage, then the MSB is “kept” by the SAR in the feedback loop by maintaining its bottom plate coupled to the reference voltage. On the other hand, if the top plate voltage is above the comparison voltage, the SAR couples and the bottom plate of the MSB capacitor to ground. The state of the MSB capacitor represents the MSB of the digital output word as a Logic
1
. The bottom plate of the second MSB is then coupled to the reference voltage and the same test is performed to determine the state of the next digital code bit. The successive approximation algorithm continues by repeating this procedure for the remaining capacitors in the array such that the voltage difference at the inputs to the comparator converge to zero. At the end of this bit cycling process, the configuration of the switches coupling the bottom plates either to Vref or Gnd represents the input sample in digital form.
Successive approximation A/D converters are useful a wide range of applications, including data acquisition, test equipment, instrumentation, cellular communications, among others. Notwithstanding, in order to improve and broaden the utility of this type of A/D converter, significant challenges remain to be addressed. These challenges include improving the device speed given a set of process constraints, reducing the coding error rate, handling metastable states and calibration of the DAC.
SUMMARY OF INVENTION
According to the principles of the present invention, high performance shift registers suitable for use in applications such as high speed charge-redistribution analog to digital converters are disclosed. According to one such embodiment, a shift register is taught which includes a plurality of shift register stages having inputs and outputs coupled to form a chain. Each stage includes enable and disable control inputs, with an output of a selected one of the stages coupled to the enable input of a stage a selected number of stages ahead in the chain and to the disable input of a stage a selected number of stages behind in the chain.
Shift registers according to the principles of the inventive concepts as well as systems and methods using the same have substantial advantages over the prior art. Among other things, such shift registers can be run at high clock rates since a decoder at the output of the shift register stages is not required. Moreover, since only a limited number of stages in the shift register are clocked at a given time, a substantial reduction in power consumption is achieved, especially at high clock rates.
REFERENCES:
patent: 5923191 (1999-07-01), Nemetz et al.
Cirrus Logic Inc.
Murphy, Esq. James J.
Wambach Margaret R.
Winstead Sechrest & Minick PC
LandOfFree
High speed, low-power shift register and circuits and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High speed, low-power shift register and circuits and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed, low-power shift register and circuits and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2993325