High speed, low power, minimal area double edge triggered...

Details High speed, low power, minimal area double edge triggered... High speed, low power, minimal area double edge triggered...

2001-09-07

2002-12-03

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S201000, C327S407000, C365S189020, C365S156000

Reexamination Certificate

active

06489825

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to flip flops and, more particularly, to a high speed, low power, minimal area double edge triggered flip flop.
2. Description of the Related Art
A rising edge triggered flip flop is a device which latches and holds the logic state of its data input signal when the rising edge of its clock input signal is detected.
Similarly, a falling edge triggered flip flop is a device which latches and holds the logic state of its data input signal when the falling edge of its clock input signal is detected.
Therefore, a double edge triggered flip flop is a device which latches and holds the logic state of its data input signal when the rising edge or the falling edge of its clock input signal is detected. Double edge triggered flip flops are commonly used in double data rate RAMs and in high speed bus interfaces.
FIG. 1A
shows a circuit diagram which illustrates a conventional double edge triggered flip flop
100
. As shown in
FIG. 1A
, flop
100
includes a clock inverter U
1
whose input
110
is connected to an external clock signal CLK. The output of clock inverter U
1
generates an inverted clock signal CLKZ.
Flop
100
also includes a first flip flop FF
1
and a second flip flop FF
2
. Flop FF
1
has a data input D
1
which is connected to an external data input
112
, receiving a data signal DATA. Flipflop FF
1
also has a clock input C
1
which is connected to external clock input
110
, receiving a clock signal CLK. Furthermore, flop FF
1
also has an output Q
1
which generates a first flop output signal FFS.
Similarly, Flop FF
2
has a data input D
2
which is connected to external data input
112
, receiving a data signal DATA. Flipflop FF
2
also has a clock input C
2
which is connected to the output of inverter U
1
, receiving an inverted clock signal CLKZ. Furthermore, flop FF
2
also has an output Q
2
which generates a second flop output signal SFS.
As further shown in
FIG. 1A
, flop
100
also includes a pair of 2-input AND gates U
2
and U
3
, and a 2-input OR gate U
4
. AND gate U
2
has an output, a first input connected to Q
1
, the output of flop FF
1
, and a second input
110
, connected to external clock input CLK.
AND gate U
3
has an output, a first input connected to Q
2
, the output of flip flop FF
2
, and a second input connected to the output of clock inverter U
1
, receiving the inverted clock signal CLKZ. OR gate U
4
has a first input connected to the output of AND gate U
2
, a second input connected to the output of AND gate U
3
, and an output connected to external output
114
, generating the flop output signal QOUT.
FIGS.
1
B
1
-
1
B
4
show timing diagrams which illustrate the operation of flop
100
. As shown in FIGS.
1
A and
1
B
1
-
1
B
4
, the rising edge of the CLK input signal on external clock input
110
causes flop FF
1
to latch the logic state of the data input signal DATA on external data input
112
. When latched, the logic state of the first flop output signal FFS, generated by flip flop output Q
1
, matches the logic state of the data input signal DATA.
When the clock rises, the logic state of the data signal DATA, at data input D
1
, is transferred to output Q
1
of flip flop FF
1
, determining the logic state of the first flop signal FFS. For example, if the data input signal DATA is a logic high when the rising edge of the clock signal CLK is detected, the first flop signal FFS will be set to a logic high.
Furthermore, the rising edge of the clock signal CLK on the second input of AND gate U
2
enables AND gate U
2
to pass the logic state of the first flop output signal FFS. At almost the same time, the second input of AND gate U
3
receives the falling edge of the inverted clock signal CLKZ output from clock inverter U
1
. This falling edge disables AND gate U
3
, causing AND gate U
3
to output a logic low.
The logic low output by AND gate U
3
enables OR gate U
4
to pass the logic state output by AND gate U
2
to QOUT, the flop output signal. Thus, when the clock rises, the logic state of the data signal DATA is transferred to flip flop FF
1
output Q
1
, which is in turn transferred through AND gate U
2
and OR gate U
4
to external output
114
, determining the logic state of the flop output signal QOUT.
Similarly, the falling edge of the clock signal CLK, on external clock input
110
, causes the rising edge of the inverted clock signal CLKZ to be output from clock inverter U
1
. The rising edge of the inverted clock signal CLKZ causes flip flop FF
2
to latch the logic state of the DATA input signal at input
112
. When latched, the logic state of the second flop signal SFS, at output Q
2
of FF
2
, matches the logic state of the data input signal DATA. When the clock falls, the logic state of the data signal DATA at data input D
2
is transferred to output Q
2
of flip flop FF
2
, determining the logic state of the second flop signal SFS. For example, if the data signal DATA is a logic low when the rising edge of the inverted clock signal CLKZ is detected, then the second flop output signal SFS will be set to a logic low.
Furthermore, the rising edge of the inverted clock signal CLKZ on the second input of AND gate U
3
enables AND gate U
3
to pass the logic state of the second flop output signal SFS. At almost the same time, the second input of AND gate U
2
receives the falling edge of clock signal CLK. This falling edge disables AND gate U
2
, causing AND gate U
2
to output a logic low.
The logic low output by AND gate U
2
enables OR gate U
4
to pass the logic state output by AND gate U
3
to QOUT, the flop output signal. Thus, when the clock falls, the logic state of the data input signal DATA is transferred to Q
2
, the output of flip flop FF
2
, which is in turn transferred through AND gate U
3
and OR gate U
4
to external output
114
, determining the logic state of the flop output signal QOUT.
One of the drawbacks of flop
100
is that it consumes a large amount of silicon area and a large amount of power. As noted above, flop
100
requires two flip flops, two AND gates, one OR gate, and one inverter.
Furthermore, the clock-to-output delay of flop
100
is excessive because the worst case propagation path includes four logic elements. Thus, when the CLK signal falls, the flop output signal QOUT cannot change state until the CLK signal propagates through inverter U
1
, and the DATA signal propagates through flip flop FF
2
, AND gate U
3
, and OR gate U
4
.
Referring to FIGS.
1
B
1
-
1
B
4
, delay time DL
1
represents the time required for the CLK signal to propagate through inverter U
1
, plus the clock-to-data delay time required for the DATA signal to propagate through flop FF
2
.
Similarly, delay time DL
2
represents the time required for the data signal to propagate through AND gate U
3
and OR gate U
4
. Thus, at a delay time DL
2
after delay time DL
1
, the logic state of the flop output signal QOUT will be determined.
From the foregoing discussion, it can be seen that the total clock-to-data output delay for flop
100
is equal to DL
1
+DL
2
, which is excessive. Thus there is a definite need for a double edge triggered flip flop which requires less propagation delay time, less power, and less silicon area.
SUMMARY OF THE INVENTION
The double edge triggered flip flop of the present invention reduces the following flop parameters: clock-to-output propagation delay, power dissipation and silicon area.
A flip flop in accordance with the present invention includes a first device which has a first input connected to a clock signal, a second input connected to a first data signal, and a first device output signal. The clock signal alternates between a first logic state and a second logic state.
The first device generates the first device output signal in response to the first data signal, when the clock signal is in the first logic state. Furthermore, the first device holds the logic state of the first device output signal in the state which is present when the clock signal transitions from its first logic stat

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