High-speed low-power low-offset hybrid comparator

Details High-speed low-power low-offset hybrid comparator High-speed low-power low-offset hybrid comparator

2001-01-05

2002-05-21

Smith, Matthew (Department: 2825)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S057000, C327S063000

Reexamination Certificate

active

06392449

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to comparator circuits and, more particularly, to high-speed CMOS only comparator circuits.
BACKGROUND INFORMATION
Comparator circuits are frequently employed in analog-to-digital conversion (ADC) circuits to compare one input signal with another. Typically, one input signal is a voltage that is compared to a reference voltage. Some comparator circuits use input capacitors as in, for example, the comparator circuit disclosed in U.S. Pat. No. 6,046,612 entitled “Self-Resetting Comparator Circuit and Method” issued Apr. 4, 2000. Although the disclosed comparator circuit represents a significant improvement to prior comparator circuits, the input capacitors cause the comparator circuit to occupy a relatively large area and have a relatively large input capacitive load.
Conventional comparator circuits that do not use input capacitors include quiescent comparators and dynamic comparators. These comparators typically have a “regenerative” stage or subcircuit that compares the input signals using a pair of MOS transistors in a common-source configuration. Quiescent comparators typically provide a continuous quiescent current in the regenerative stage to bias the common-source node, which causes the quiescent comparator to continuously dissipate a significant amount of current while the circuit is powered. Further, the speed of regeneration is typically directly proportional to the magnitude of the quiescent current. Therefore, a high-speed quiescent comparator generally has a relatively high power dissipation.
Dynamic comparators do not use a quiescent current, but rather employ a dynamic current to briefly activate the regenerative stage to compare the input signals. Therefore, dynamic comparators tend to have a lower power dissipation than quiescent comparators. However, dynamic comparators typically have a delay to allow the dynamic current to charge the common-source node before starting regeneration. This delay undesirably reduces the regeneration speed. Further, regeneration causes relatively large transient currents to flow through the source-coupled MOS transistors in the regenerative stage. These transient currents can cause significant dynamic errors in the differential output signal generated by the regenerative stage, which are in addition to the static errors caused by mismatch of the devices in the regenerative stage.
SUMMARY
In accordance with aspects of the present invention, a comparator circuit is provided. In one aspect of the present invention, the comparator circuit includes a regenerative stage that uses a relatively small quiescent current combined with a relatively large dynamic current to charge a common-source node in the regenerative stage. Using the relatively small quiescent current allows the comparator circuit to dissipate less power than the aforementioned quiescent comparators. However, by providing the quiescent current, the common-source node in the regenerative stage is maintained near the desired charged level. This maintenance of the common-source node significantly reduces the delay needed before regeneration can proceed, compared to the aforementioned dynamic comparators.
In a further aspect of the present invention, the comparator circuit includes a dynamic bandgap reference that provides a biasing signal to the regenerative stage that increases the quiescent current with increased frequency of a clock signal driving the dynamic bandgap reference. This aspect can be advantageously used to adjust the regeneration speed. That is, by increasing the quiescent current, the regeneration speed is increased, but at the cost of higher power dissipation. Some applications may have low-speed and high-speed operational modes. This aspect of the present invention allows the comparator circuit to save power during low-speed mode operation by appropriate control of the dynamic bandgap reference.
In another aspect of the present invention, the comparator circuit includes an input isolation circuit to eliminate charge kick-back to the input signal lines from the source-coupled MOS transistors. Shortly after regeneration begins, the isolation circuit isolates the gates of the source-coupled pair from the input signals. The isolation circuit provides fixed reference signals to the gates of the source-coupled pair, isolated from the input lines that carry the input signals. For example, with a PMOS source-coupled pair, switches are opened to disconnect the gates of the source-coupled pair from the lines carrying the input signals. In addition, the gates are connected to the ground bus, thereby preventing the gate voltages from becoming negative. The isolation circuit allows the comparator circuit to have a more consistent and fast regeneration speed.


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