High speed low power input buffer

Details High speed low power input buffer High speed low power input buffer

2000-08-28

2002-06-18

Smith, Matthew (Department: 2825)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S056000

Reexamination Certificate

active

06407588

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuits. More particularly, it pertains to differential amplifiers including input buffers.
BACKGROUND OF THE INVENTION
Differential amplifiers are commonly used in memory devices as input buffers to couple data signals between a memory array and data terminals of the memory devices. Generally, one common problem with these input buffers is the setting of a switching point voltage to maximize the switching response of the input buffers. Switching point voltage refers to the point at which the input and output voltages are transitioning from a high state-to-low state or a low state-to-high state. If the switching point voltage goes too high, the bits of data coming out of the input buffer will have a good low noise margin, but will not have a high noise margin similarly, if the switching point voltage goes too low, the bits of data will have a good high noise margin, but will not have a good low noise margin. If the switching point voltage is too high or too low, the bits of data coming out of the input buffer can be distorted. For example, if we were to input a voltage in a digital wave form having a sloping rise and fall times like a triangular wave, and if the switching point voltage is too high or too low, the bits of data coming out of the input buffer can be of varying widths and can cause timing problems in the input buffer.
Thus, there is a need for an input buffer that can automatically establish a switching point voltage that maximizes the high and low noise margins of an integrated circuit. There is also a need for input buffers used in memories of computers to transfer data at a faster rate using low power. Therefore, there is also a need for a low power high-speed input buffer that is capable of operating at high speeds, while using low power.
SUMMARY OF THE INVENTION
The input buffer of the present invention provides, among other things, provides a mechanism to accurately establish a switching point voltage that maximizes the high and low noise margins of an integrated circuit, while using a low power. Also the input buffer is capable of operating at high speeds. According to one embodiment, the input buffer has an input stage providing a switching point voltage based on a predetermined switching point set between first and second reference voltages that maximizes the high and low noise margins of the input buffer. The input buffer further includes an output stage. The output stage is coupled to the input stage. The output stage receives the switching point voltage from the input stage and amplifies the switching point voltage to a full logic level voltage.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims and their equivalents. Other aspects of the invention will be apparent on reading the following detailed description of the invention and viewing the drawings that form a part thereof.


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