Oscillators – With frequency adjusting means – With voltage sensitive capacitor
Reexamination Certificate
2002-09-13
2004-08-24
Mis, David (Department: 2817)
Oscillators
With frequency adjusting means
With voltage sensitive capacitor
C331S179000, C327S105000, C327S106000, C327S107000
Reexamination Certificate
active
06781473
ABSTRACT:
BACKGROUND OF THE INVENTION
This application relates generally to signal synthesis and more specifically to generating sinusoidally varying signals, such as sine and cosine wave signals, using a numerically controlled oscillator.
Numerically controlled oscillators (NCOs) are commonly employed in electronic systems requiring periodic signal references. Modulators and demodulators are examples of electronic systems that often require periodic signals and periodic signal generators, such as NCOs. Modulation includes processes in which an information signal is superimposed onto a carrier wave, such as a sinusoidally varying signal generated by an NCO. Well known analog modulation techniques include, for example, amplitude modulation (AM), frequency modulation (FM), and phase modulation (PM) among others. Well known digital modulation techniques include, for example, pulse amplitude modulation (PAM) and pulse width modulation (PWM) among others. Once modulated, carrier waves are transmitted to a receiver; at the receiver location, the information signal superimposed onto the carrier wave is extracted via a demodulation process in a demodulator. Demodulators often use periodic signals generated by NCOs as reference signals for locking onto the carrier wave during a demodulation process.
FIG. 1
is a simplified schematic of a known communication demodulator
100
incorporating an NCO
115
, which generates a periodic signal used in a demodulation process. As shown, communication demodulator
100
receives a modulated data signal
120
carrying an information signal. The periodic signal generated by the NCO
115
and the modulated data signal are each received by a mixer-multiplier circuit
125
that separates the information signal from the modulated data signal
120
. The output of the mixer-multiplier
125
is transmitted to a filter circuit
130
that filters out the carrier wave and outputs an information signal
135
(i.e., demodulated data).
FIG. 2
is a simplified schematic of NCO
115
, showing the NCO in greater detail. NCO
115
is of a type commonly known and used in industry, and has numerous shortcomings that will be discussed. The NCO
115
includes a phase accumulator
205
for generating numerical sequences, such as memory addresses. In the phase accumulator a fixed number, called a phase increment
210
, is summed with a delayed feedback number
215
. The delayed feedback number
215
is controlled by a delay circuit
220
(e.g., a flip-flop) that clocks the delayed feedback number
215
into a modulo N adder
225
. A system clock
230
provides clock pulses to the delay circuit for delaying the feedback. The numerical sequence output from the phase accumulator is then mapped to the desired periodic signal
235
(i.e., sine wave/sinusoidal signal) by peripheral logic
245
using a look-up table implemented in a memory
240
, such as a read only memory (ROM). The memory
240
is configured to store a quarter of sine wave
235
in order to reduce memory size.
FIG. 3A
shows a sine wave divided into quarter portions, such as those stored in memory
240
. Although the memory
240
stores an incomplete sinusoid, peripheral logic
245
(see
FIG. 2
) provides for the full cycle of the sinusoid to be constructed. Consequently, the NCO is able to generate a single sinusoidal signal
235
as the desired output.
An additional signal, such as a quadrature signal (90° out of phase), according to known NCO designs, requires a redundant memory for storing another sine wave quadrant and redundant peripheral logic for manipulating the other quadrant.
FIG. 3B
shows first and second sinusoidal signals
300
and
305
. Sinusoidal signal (i.e., sine wave)
305
is said to be in quadrature with, or to be the quadrature signal of sinusoidal signal (i.e., cosine wave)
300
.
FIG. 4
is a simplified schematic of a typical NCO
405
providing two sinusoidally varying signals
235
a
and
235
b
, with signal
235
b
being the quadrature signal of signal
235
a
. In order to generate the two signals, NCO
405
includes two memories
240
a
and
240
b
, and two peripheral logic circuits
245
a
and
245
b
. It is noted that a numeral scheme similar to that used in
FIG. 2
is used for similar features shown in FIG.
4
. Since NCO
405
requires redundant circuitry to generate the two signals
235
a
and
235
b
, the footprint (area occupied on a semiconductor chip) of the NCO
405
is relatively large. Alternatively, an additional output (i.e., signal
235
b
) may be generated with additional time-multiplexing circuitry (not shown), which tends to be costly and slow. For example, generating two sinusoidally varying signals from a single sinusoidally varying signal using time multiplexing techniques takes at least twice the amount of time required to generate a single sinusoidally varying signal. Further yet, known NCO
500
(see
FIG. 5
) providing multiple pairs of channel outputs
510
(each pair is labeled with a numerical suffix), require a pair of memories
520
(each pair is labeled with a numerical suffix) for each pair of channel outputs. Such NCO configurations requiring redundant systems and circuits are relatively costly to implement in multi-channel modulation and/or demodulation systems.
As can be understood from the above discussion, conventional NCOs use relatively large memories having relatively large footprints and relatively high cost to implement look-up tables for storage of quarter sine waves. Further, known multi-channel NCO designs add extra cost due to the use of redundant circuits. Accordingly the industry continues to strive to create low gate count (i.e., small footprint, low cost, low circuit redundancy), multi-channel NCOs for signal synthesis as well as other applications.
SUMMARY OF THE INVENTION
The present invention provides methods and apparatus for multi-channel output NCOs that do not engender the problems described above. NCOs characteristic of the present invention provide for reduced memory size and streamlined logic for implementing a high-speed and lower-power design with multi-channel outputs.
In accordance with an aspect of the present invention, a numerically controlled oscillator (NCO) comprises a phase accumulator configured to generate a periodic multi-bit signal at a given frequency; a first memory configured to store an octant of a sinusoidal waveform; a second memory configured to store a complementary octant of the sinusoidal waveform; and a control circuit, responsive to at least a portion of the phase accumulator signal and coupled to the first and second memories, the control circuit configured to access the first and second memories in parallel and construct respective sine and cosine waves at the given frequency. The invention can also be used to generate periodic waveforms other than sinusoidal, so long as the waveform has the symmetry property that the entire waveform can be reconstructed from a pair of complementary octants.
In some embodiments, the control circuit includes a memory address generator, responsive to a first subset of bits from the phase accumulator signal, configured to generate addresses for said first and second memories, said addresses providing for access in a normal sequence of increasing numerical values or access in a reverse sequence of decreasing numerical values; an octant-selector circuit, responsive to a second subset of bits from the phase accumulator signal, the octant-selector circuit being connected to receive outputs from the first and second memories and configured to use one of the first and second memory outputs to construct an unsigned-sine wave and to use the other of the first and second memory outputs to construct an unsigned-cosine wave; and a selective-negation circuit, responsive to a third subset of bits from the phase accumulator signal, the selective negation circuit being connected to receive the unsigned-sine wave and the unsigned-cosine wave from the octant-selector circuit and configured to generate the sine wave and the cosine wave therefrom.
In accordance with an aspect of the pres
Chiu John S
Kasetti Sricharan
Stenerson Roger
Zhang Wei-Min
BroadLogic Network Technologies Inc.
Mis David
Townsend and Townsend / and Crew LLP
LandOfFree
High-speed low-power implementation for multi-channel... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High-speed low-power implementation for multi-channel..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-speed low-power implementation for multi-channel... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3350022