High-speed low-power flip-flop

Details High-speed low-power flip-flop High-speed low-power flip-flop

1989-06-02

1991-07-30

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307291, 377117, H03K 3284, H03K 3289

Patent

active

050362178

ABSTRACT:
A master-slave flip-flop having a first bistable cell and a control circuit coupled to that first cell for changing the binary state of the cell in response to a set of complementary data inputs and a clock signal. The slave portion of the flip-flop includes a second bistable cell that is coupled to the first cell and a second control circuit for changing the state of the second cell in response to the output of the first cell and to a clock signal. The flip-flop is intended to be implemented using CMOS technology, and is capable of performing at frequencies greater than a gigahertz with low power consumption. The circuit configuration is highly symmetric, so that the master and slave portions may be interchanged.

REFERENCES:
patent: 3539836 (1966-12-01), Seelbach
patent: 3728561 (1973-04-01), Brocker
patent: 4484087 (1984-11-01), Mazin
patent: 4626706 (1986-12-01), Allen
patent: 4656368 (1987-04-01), McCombs
patent: 4913007 (1980-03-01), Tietz

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