High speed low power fixed-point multiplier and method thereof

Details High speed low power fixed-point multiplier and method thereof High speed low power fixed-point multiplier and method thereof

2011-03-22

2011-03-22

Do, Chat C (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S620000

Reexamination Certificate

active

07912891

ABSTRACT:
Provided are a high speed and low power fixed-point multiplier and method thereof. The multiplier includes: a partial product calculation unit for dividing input data into a plurality of bit groups, each bit group having a predetermined number of bits, generating partial products by independently multiplying a fixed coefficient for each bit group, and summing partial products included in a corresponding bit group, to thereby generate a summed partial products; and an adding unit for adding the summed partial products of each bit group generated from the partial product calculation unit.

REFERENCES:
patent: 4868778 (1989-09-01), Disbrow
patent: 5255216 (1993-10-01), Blanz et al.
patent: 5530664 (1996-06-01), Tsubata et al.
patent: 5841684 (1998-11-01), Dockser
patent: 5958000 (1999-09-01), Jiang
patent: 6223197 (2001-04-01), Kosugi
patent: 6438569 (2002-08-01), Abbott
patent: 7024445 (2006-04-01), Qi
patent: 7769797 (2010-08-01), Cho et al.
patent: 2001/0037352 (2001-11-01), Hong
patent: 2003/0120694 (2003-06-01), Qi
patent: 2005/0050134 (2005-03-01), Winterrowd
patent: 09-097166 (1997-04-01), None
patent: 1997-0029021 (1997-06-01), None
patent: 1020000061675 (2000-10-01), None
patent: 1020000066326 (2000-11-01), None
patent: 1019990003926 (2001-03-01), None
patent: 1020060044102 (2006-05-01), None
Author: Ferguson et al.; Title: “A Multiplier with Redundant Operands”; Date: 1999; URL: http://ieeexplore.ieee.org/search/srchabstract.jsp?tp=&arnumber=831921.
Author: Huang et al.; Title: “High-Performance Low-Power Left-to-Right Array Multiplier Design”; Date: Mar. 2005; URL: http://arith.cs.ucla.edu/publications/HuangErc-LowPowMult-TC05.pdf.
Hu, A. et al., “Comparison of constant coefficient multipliers for CSD and Booth recoding,” The 14th International Conference on Microelectronics, pp. 66-69, Dec. 2002.
Pai, Cheng-Yu et al., “Low-power constant-coefficient multiplier generator,” 14th Annual IEEE International ASIC/SOC Conference, Proceedings. pp. 185-189, 2001.
Al-Khalili, A.J. et al., “32-bit constant (k) coefficient multiplier,” Proceedings of IEEE Region 10 International Conference on Electrical and Electronic Technology, vol. 1, pp. 306-308, 2001.
Korean Notice of Patent Grant dated Sep. 27, 2007 for the corresponding application KR 10-2006-0055076.
Sang-Min Hong et al, “A 32x32-b Multiplier Using A New Method to Reduce a Compression Level of Partial Products” The Paper of Electronic Engineering Conference, vol. 40, No. 6. pp. 69-80, Jun. 2003.

Affiliated with

Also associated with

Rating

High speed low power fixed-point multiplier and method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed low power fixed-point multiplier and method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed low power fixed-point multiplier and method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2698795