High-speed/low power finite impulse response filter

Details High-speed/low power finite impulse response filter High-speed/low power finite impulse response filter

2000-03-16

2004-02-03

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06687722

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to methods and apparatuses for performing finite impulse response (FIR) filter operations, and more particularly to a method and apparatus for performing a finite impulse response filter operation that consumes low power without degrading the FIR filter's performance.
Modem applications require low cost chips containing integrated FIR filters. The widely known and understood FIR filter essentially performs a sum-of-products computation. In Very Large Scale Integration architectures, a fast FIR filter normally contains a set of multipliers to weight the input samples by the filter coefficients and a set of adders to accumulate the multiplier results. Given that hardware multipliers are essentially the addition of multiple partial products, the multiplier is often combined with the adders to make the FIR filter structure.
A well-known technique for accumulating several numbers is to use a carry-save format. A carry-save adder (CSA) does not propagate the carry in the normal manner but rather stores the carry in a separate vector. Carry-save adders are faster and more efficient than carry-propagate adders (CPA). Carry-save adders are normally configured with each adder taking four operand vectors and producing two result vectors (a sum and a carry vector).
In
FIG. 1
, carry-save adders
1
are used to add together the outputs, of several multipliers
2
, each of which outputs a result in carry-save format. Each carry-save adder
1
adds two numbers in carry-save format—one from the multiplier
2
and the other from the previous carry-save adder.
1
, the output of which is stored in flip-flops
4
. In
FIG. 1
, the carry-save adders
1
are indicated as “4-2” meaning four inputs and two outputs At the output of the filter there are only two vectors to be added together, at which point a single carry-propagate adder
3
is used to compute the final result. In
FIG. 1
, the vectors are partitioned into most significant bit (MSB) and least significant bit (LSB) components for later comparison.
In high-speed filters, the transposed FIR form is commonly used to achieve the highest performance because the series adders are populated with flip-flops
4
to enable each multiply-add operation to take a complete clock cycle to execute. This filter structure contains flip-flops
4
in the output accumulation path. Because the results are stored in carry-save format, there are actually two flip-flops
4
per bit of precision in the output path (one for the sum bit and one for the carry bit). The flip-flops
4
are shown as registers in FIG.
1
and marked Clsb/Cmsb and Slsb/Smsb for carry least significant bit/most significant bit and sum least significant bit/sum most significant bit, respectively.
The advantages with carry-save arithmetic include reduced propagation delay, reduced integration area and reduced power dissipation because one adder is eliminated at each multiplier output. A disadvantage is that more flip-flops are needed when pipelining the carry-save filter accumulation paths. These additional flip-flops lead to increased power consumption mainly due to increased current drain on the source of the clock signal.
The present invention is therefore directed to the problem of developing a method and apparatus for performing an FIR filter operation without consuming much power and without any degradation in filter performance while maintaining reduced propagation delay.
SUMMARY OF THE INVENTION
The present invention solves this problem by using a partial carry-save format for the filter output representation thereby reducing the number of flip-flops or registers and hence the power. By replacing the least significant bit processing section on the output side of the finite impulse response (FIR) filter with a combined carry-save adder and carry-propagate adder followed by a single register rather than two registers or flip-flops, the present invention reduces the load on the clock and achieves a reduced propagation delay.
To further improve the performance of the FIR filter, the present invention employs a simpler carry-save adder than heretofore was possible by using a single register at the input to each of the carry-save adders in the least significant bit portion rather than two registers or flip-flops, one for the carry and one for the sum. The combination of a reduction of half of the registers or flip-flops and a concomitant replacement of a simpler carry-save adder for each of the carry-save adders results in a significant improvement in the overall filter performance.


REFERENCES:
patent: 5751619 (1998-05-01), Agarwal et al.
patent: 5761106 (1998-06-01), Crocker
patent: 5777679 (1998-07-01), Cheney et al.
patent: 5974435 (1999-10-01), Abbott
patent: 6360189 (2002-03-01), Hinds et al.
patent: 6438569 (2002-08-01), Abbott

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