High-speed low-power delayed clock generator

Details High-speed low-power delayed clock generator High-speed low-power delayed clock generator

1982-09-16

1985-06-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307481, 307578, 307269, H03K 1704, H03K 17687

Patent

active

045217017

ABSTRACT:
A clock circuit for producing a high-level delayed clock output following an input clock employs an output transistor and pull-down transistor controlling an output node in response to the voltage on a drive node. The input clock is applied to this drive node by a decoupling arrangement, consisting of two series transistors. The first transistor isolates the input charge on a holding node, and the second of the series transistors transfers the charge to the drive node after the desired delay. The output node is held at zero until after the delay, with no unwanted voltage rise, and no d.c. power loss. A large capacitive load can be driven.

REFERENCES:
patent: 4061933 (1977-12-01), Schroeder et al.
patent: 4289973 (1981-09-01), Eaton, Jr.
patent: 4354123 (1982-10-01), Eaton, Jr.
patent: 4379974 (1983-04-01), Plachno
patent: 4401904 (1983-08-01), White, Jr. et al.
patent: 4431927 (1984-02-01), Eaton, Jr. et al.
Arzubi et al., "Bootstrap Driver Stage", IBM Tech. Disc. Bull., vol. 23, No. 9, Feb. 1981, pp. 4185-4186.

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