High-speed, low-power continuous-time CMOS current comparator

Details High-speed, low-power continuous-time CMOS current comparator High-speed, low-power continuous-time CMOS current comparator

2000-10-11

2001-11-20

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S080000, C327S109000, C326S082000, C326S083000

Reexamination Certificate

active

06320427

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a complementary metal-oxide-semiconductor (CMOS) current comparator. More specifically, the present invention relates to a CMOS current comparator featuring shortened response delay time, low power consumption, smaller area and enhanced process robustness.
2. Description of the Related Art
In recent years current-mode signal manufacturing processes using CMOS technology has gained great interest. Using this approach, many analog CMOS circuits have been designed with the objectives of smaller area, higher speed and lower supply voltage. Moreover, it is compatible with digital process thereby allowing current-mode circuit technology to be considered an viable alternative to voltage-mode circuit technology in high speed, low-power applications. As a fundamental component of current-mode analog systems, a current comparator can be used, for example, in analog-to-digital (A/D) converters, oscillators, current to frequency converters and Very-Large-Scale-Integrated (VLSI) circuit neural networks.
For high-speed applications, a number of high-performance continuous-time CMOS current comparators have been purposed in the past few years.
FIG. 1
represents a current comparator proposed in Electronics Letters, Vol.28, No.3, pp.310-312, 1992 by Traff. The current comparator proposed by Traff uses a source-follower (M
1
and M
2
) as an input stage and a CMOS inverter as a positive feedback thereby enabling lower input resistance and shorter response time when compared with the original current comparator based on current mirrors. However, in pursuit of dynamic response from smaller input current levels, there temporarily exists a deadband region in which the two input transistors (M
1
and M
2
) are both turned off to induce higher input resistance. Hence, achievement of a decrease in input current without this side-effect would dramatically increase the dynamic response of the current comparator provided by Traff.
FIG. 2
depicts a current comparator designed to solve this problem as proposed by Tang in Electronics Letters, Vol.30, No.1, pp.5-6, 1994. Here, Tang changes the biasing scheme of the input stage from class B operation to class AB operation by adding two triode-operation transistors (M
3
and M
4
). The intent being reduction of the deadband region and decreased response time for small input current. However, this circuit structure is overly complicated. Four additional current sources (I
1
—I
4
) are needed for constructing the biasing circuit to enable enhanced power dissipation. Moreover, the process deviations have substantial negative effects on the current comparator as its performance is closely related to the value of the four current sources. Furthermore, the bulks of two bias transistor, M
3
and M
4
, are connected to their sources, rather than to ground and power, respectively. Hence, a complicated twin-tub CMOS manufacturing process is needed to implement Tang's circuit design.
FIG. 3
represents the current comparator proposed by Min as published in Electronics Letters, Vol.34, No.22, pp.2074-2076, 1998. In
FIG. 3
, the current comparator comprises three current-source inverting amplifiers and a CMOS inverter. A resistive feedback network is added to the first current-source inverting amplifier in an effort to decrease input resistance. Although this circuit exhibits low response time and good process immunity, its resolution is limited by the bias current as high-resolution applications require large bias current and consume substantially more power. Moreover, because current-source amplifiers are utilized, power consumption does not decrease as input current increases.
SUMMARY OF THE INVENTION
Therefore, an objective of the present invention is to provide a new continuous-time current comparator design solution featuring shortened response delay time, lower power consumption, smaller area and enhanced process robustness.
The present invention achieves the above-indicated objectives by providing a current comparator comprising a CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. The CMOS complementary amplifier receives an input current from an input node which generates an output voltage at a corresponding output node. The CMOS complementary amplifier is comprised of an N-type metal oxide semiconductor field effect transistor (NMOS) and a P-type metal oxide semiconductor field effect transistor (PMOS) connected in series. Control gates on both the NMOS and PMOS are connected to form the input node. NMOS and PMOS drain electrodes are also coupled to the output node. The CMOS complementary amplifier further has a resistive feedback circuit which is connected between the input and output nodes. The two resistive-load amplifiers are connected in cascade form to receive and amplify output voltage from the CMOS complementary amplifier. The result being a correspondingly output of amplified voltage. The two CMOS inverters are also connected in cascade form to receive the amplified voltage and correspondingly output rail-to-rail result signal.
Lastly, simulation results show the current comparator, according to the present invention, provides a better speed/power ratio when compared to current comparators of the existing art.


REFERENCES:
patent: Re. 31749 (1984-11-01), Yamashiro
patent: 4071830 (1978-01-01), Huntington
patent: 4309665 (1982-01-01), Yamashiro
patent: 5041744 (1991-08-01), Sakai et al.
patent: 5329190 (1994-07-01), Igarashi et al.

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