High speed low power content addressable memory

Details High speed low power content addressable memory High speed low power content addressable memory

2001-03-22

2002-02-19

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S203000

Reexamination Certificate

active

06349049

ABSTRACT:

BACKGROUND
1. Field of Invention
This invention relates generally to semiconductor memory devices and specifically to a content addressable memory.
2. Description of Related Art
A CAM includes an array of memory cells arranged in a matrix of rows and columns. Each memory cell stores a single bit of digital information, i.e., either logic zero or logic one. The bits stored within a row of memory cells constitute a CAM word. During compare operations, a comparand word is received at appropriate input terminals of a CAM device and driven into the CAM array using compare lines to be compared with all the CAM words in the device. For each CAM word that matches the comparand word, a corresponding match line signal is asserted to indicate a match condition. If the comparand word matches more than one of the CAM words, the match line corresponding to each of the matching CAM words is asserted, and a “multiple match” flag is also asserted to indicate the multiple match condition. The match line signals from each CAM word are combined in a priority encoder to determine the index or address of the highest-priority matching CAM word.
In early CAM architectures, the match result for each CAM word is determined by a dynamic NOR of individual bit comparison results for that row. For example, in a dynamic NOR match circuit, each CAM cell controls a corresponding match transistor connected in parallel between the match line and ground potential. Prior to a compare operation, the match line is typically pre-charged to a supply voltage (e.g., V
DD
). During the compare operation, a comparand word is compared to data stored in each row. For any given row, if any of the individual bit comparisons produce a mismatch condition, the match transistor of the corresponding CAM cell turns on and discharges the match line to ground potential to indicate the mismatch condition. Conversely, if all CAM cells in a row produce a match condition, the match transistors do not turn on, and thus the match line remains charged (e.g., at V
DD
). Since each match line is discharged in response to a mismatch condition, CAM architectures having a dynamic NOR match circuit incur two match line transitions (e.g., one to pre-charge and another to discharge) per mismatched word per compare operation. Accordingly, dynamic NOR match circuits typically have excessive power dissipation, since no more than one match is typically expected per compare operation.
To reduce such power dissipation, the dynamic NOR match circuit may be replaced by a dynamic NAND match circuit, where the match transistors of CAM cells in each row are connected in series between the supply voltage and the match line. Prior to a compare operation, the match line is typically discharged (e.g., to ground potential). During the compare operation, if all of the individual bit comparisons produce a match, all the match transistors turn on and pull or charge the match line toward the supply voltage to indicate the match condition. Conversely, if any of the individual bit comparisons produce a mismatch condition, the match transistor of the corresponding mismatching CAM cell does not turn on, thereby preventing the match line from charging toward the supply voltage. Accordingly, since there is typically only one matching row per compare operation, only one match line is typically charged toward the supply voltage per compare operation, thereby reducing power dissipation over NOR match circuits.
However, because of a phenomena commonly known as the body effect, stacked NAND structures such as NAND match circuits are typically slower than NOR structures. Further, parasitic capacitances associated with the series-connected match transistors of dynamic NAND match circuits may result in significant loading which, in turn, undesirably slows the charging of the match line. Accordingly, there is a need to improve the speed of NAND match detection circuits.
SUMMARY
A CAM architecture is disclosed that may increase performance over conventional CAM devices. In accordance with the present invention, one or more boost circuits are included within each row of CAM cells to increase the charging rate of its match line during match conditions. The CAM cells in each row control corresponding match transistors connected in series between a supply voltage and a match line. The match transistors collectively form a NAND match circuit. A boost circuit having power terminals connected to the supply voltage and to ground potential is coupled to a midpoint of the NAND match transistor chain. Prior to compare operations, the match line may be discharged using the boost circuit. During compare operations, each match transistor turns on if there is a match in the corresponding CAM cell. If all CAM cells match, all match transistors turn on and pull the match line toward the supply voltage. As the voltage at the midpoint of the match line reaches a threshold, the boost circuit provides an additional charging path for the match line to more quickly charge the match line during the match condition. In this manner, the boost circuit increases the speed with which the match conditions propagate along the NAND match transistor chain. Conversely, if any CAM cell mismatches, its match transistor turns off and isolates the match line from the supply voltage, thereby forcing the match line to remain in its discharged state.
In one embodiment, each CAM row includes a plurality of first and second CAM cells and associated first and second boost circuits. Each CAM cell has a match node coupled to the gate of a corresponding match transistor. The match transistors corresponding to the first CAM cells are connected in series between the supply voltage via an evaluate transistor and a first node, to which the first boost circuit is also coupled. The match transistors corresponding to the second CAM cells are connected in series between the first node and a second node, to which the second boost circuit and match line are also coupled. If there is a match condition in all the first CAM cells, the first boost circuit turns on and quickly charges the first node to the supply voltage. If there is also a match condition in all the second CAM cells, the second boost circuit turns on and quickly charges the match line to the supply voltage to indicate the match condition. In this manner, the first and second boost circuits increase the charging rate of the match line when there is a match condition.


REFERENCES:
patent: 6170891 (2000-11-01), Nataraj
patent: 6195278 (2001-02-01), Catlin et al.
patent: 6243280 (2001-05-01), Wong et al.
K. Schultz et al, “Fully-Parallel 25 MHz 2.5 Mb CAM,” IEEE 1998 SA 21.1-21.12.

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