High speed, low power comparator

Details High speed, low power comparator High speed, low power comparator

2006-10-31

2006-10-31

Nguyen, Linh (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S155000

Reexamination Certificate

active

07129865

ABSTRACT:
A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

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