High speed, low power comparator

Details High speed, low power comparator High speed, low power comparator

2002-08-23

2004-04-27

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06727839

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high speed, low power comparators.
2. Background Art
Commercialization of the Internet has proven to be a mainspring for incentives to improve network technologies. Development programs have pursued various approaches including strategies to leverage use of the existing Public Switched Telephone Network and plans to expand use of wireless technologies for networking applications. Both of these approaches (and others) entail the conversion of data between analog and digital formats. Therefore, it is expected that analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) will continue to perform critical functions in many network applications.
Because ADCs find uses in a wide variety of applications, design of these circuits has evolved along many paths to yield several distinct architectures, including “delta sigma,” “successive approximation,” “pipelined,” “subranging,” “folding,” and “flash.” Comparators are the basic building block in each of these designs, and some architectures—such as pipelined, subranging, folding, and flash—use an array of comparators.
For example,
FIG. 1
is a block diagram of an exemplary conventional two-bit flash ADC
100
. ADC
100
comprises a first comparator “A”
102
, a second comparator “B”
104
, a third comparator “C”
106
, a priority encoder
108
, a first resistor “R
1
”
110
, a second resistor “R
2
”
112
, a third resistor “R
3
”
114
, and a fourth resistor “R
4
”
116
. Each of R
1
110
, R
2
112
, R
3
114
, and R
4
116
has the same measure of resistance. R
1
110
, R
2
112
, R
3
114
, and R
4
116
are connected in series between an analog ground “V
AG
”
118
and a first supply voltage “V
DD
”
120
. (Alternatively, analog ground V
AG
118
can be replaced by a second supply voltage “V
SS
”.) R
1
110
is connected between V
AG
118
and a first node “N
1
”
122
. R
2
112
is connected between N
1
122
and a second node “N
2
”
124
. R
3
114
is connected between N
2
124
and a third node “N
3
”
126
. R
4
116
is connected between N
3
126
and V
DD
120
. In this configuration, the voltage at N
1
122
(the reference voltage of comparator A
102
) is equal to V
DD
/4, the voltage at N
2
124
(the reference voltage of comparator B
104
) is equal to V
DD/
2, and the voltage at N
3
126
(the reference voltage of comparator C
106
) is equal to
3
V
DD
/4.
The inverting terminals of comparators A
102
, B
104
, and C
106
are connected to, respectively, N
1
,
122
, N
2
124
, and N
3
126
. An analog signal “x”
128
is received at an input
130
, which is connected to the noninverting terminals of comparators A
102
, B
104
, and C
106
. A quantized signal is produced at the output terminal of each comparator. Quantized signals “w
1
”
132
, “w
2
”
134
, and “w
3
”
136
are produced at the output terminals of, respectively, comparators A
102
, B
104
, and C
106
. Each quantized signal has a voltage with a value “LOW” or a value “HIGH” depending upon whether a corresponding value of the voltage of analog signal x
128
is less than (or equal to) or greater than the voltage at the inverting terminal of the corresponding comparator (i.e., the reference voltage of the comparator). For example, when the value of the voltage of analog signal x
128
is less than or equal to V
DD/
4, the values of the voltages of w
3
136
, w
2
134
, and w
1
132
are equal to, respectively, LOW, LOW, and LOW. When the value of the voltage of analog signal x
128
is less than or equal to V
DD
/2, but greater than V
DD
/4, the values of the voltages of w
3
136
, w
2
134
, and w
1
132
are equal to, respectively, LOW, LOW, and HIGH. When the value of the voltage of analog signal x
128
is less than or equal to 3V
DD
/4, but greater than V
DD
/2, the values of the voltages of w
3
136
, w
2
134
, and w
1
132
are equal to, respectively, LOW, HIGH, and HIGH. When the value of the voltage of analog signal x
128
is less than or equal to V
DD
, but greater than 3V
DD
/4, the values of the voltages of w
3
136
, w
2
134
, and w
1
132
are equal to, respectively, HIGH, HIGH, and HIGH.
The output terminals of comparators A
102
, B
104
, and C
106
are connected to priority encoder
108
. Quantized signals w
1
132
, w
2
134
, and w
3
136
are received by priority encoder
108
, which processes them to produce, at an output
138
, a two-bit digital signal “y” comprising a least significant bit (LSB) signal “y
1
”
140
and a most significant bit (MSB) signal “y
2
”
142
.
The skilled artisan will appreciate that, with additional comparators and resistors and by using a priority encoder capable of processing additional quantized signals, flash ADC
100
can be modified so that digital signal y comprises more than two bit signals. Alternatively, flash ADC
100
can be modified so that digital signal y comprises one bit signal.
Implementations of comparators A
102
, B
104
, and C
106
often use current-mode latch circuits.
FIG. 2
is a schematic diagram of an exemplary conventional current-mode latch circuit
200
that can be used in an implementation of any of comparators A
102
, B
104
, or C
106
. Latch circuit
200
comprises a cross-connected pair of transistors
202
connected between a reset switch
204
and first supply voltage V
AG
118
. Preferably, cross-connected pair
202
comprises a first NMOSFET (n-channel Metal Oxide Semiconductor Field Effect Transistor) “M
1
”
206
and a second NMOSFET “M
2
”
208
. Ideally, M
1
l
206
and M
2
208
are matched transistors. Preferably, each of M
1
206
and M
2
208
has a gain greater than one. However, cross-connected pair
202
can function if the product of the individual gains of M
1
206
and M
2
208
(i.e., the loop gain) is greater than one. The gate terminal of M
2
208
is connected to the drain terminal of M
1
206
at a first port “N
4
”
210
. The gate terminal of M
1
206
is connected to the drain terminal of M
2
208
at a second port “N
5
”
212
. The source terminals of M
1
206
and M
2
208
are together connected to analog ground V
AG
118
. Preferably, reset switch
204
comprises a third NMOSFET “M
3
”
214
. The source terminal of M
3
214
is connected to the drain terminal of one of M
1
206
or M
2
208
; the drain terminal of M
3
214
is connected the drain terminal of the other of M
1
206
or M
2
208
. A clock waveform “Ck”
216
is applied to the gate terminal of M
3
214
. Ck
216
cycles between an “UP” voltage and an “DOWN” voltage at a sampling frequency.
The skilled artisan will appreciate that M
1
206
, M
2
208
, and M
3
214
can also be realized in other field effect, junction, or combination transistor technologies. In general, reset switch
204
can be realized in a variety of switch technologies, including microelectromechanical embodiments. Latch circuit
200
can also be used for other applications.
For each latch circuit
200
in ADC
100
, quantized signal “w” (e.g., w
1
132
, w
2
134
, or w
3
136
) is produced as an output voltage at N
4
210
or N
5
212
. Latch circuit
200
is often preceded by an input stage (not shown) that includes a differential amplifier so that the voltage of analog signal x
128
, applied at the noninverting terminal of the comparator, can be compared with the voltage at the inverting terminal of the comparator. For example, the voltage of analog signal x
128
is compared with V
DD
/4, for comparator A
102
; V
DD
/2, for comparator B
104
; and 3V
DD
/4, for comparator C
106
.
For each latch circuit
200
in ADC
100
, the input stage produces a differential current signal comprising a first current signal “i
1
”
218
and a second current signal “i
2
”
220
. First and second current signals i
1
218
and i
2
220
each comprise a bias current “i
b
” and a signal current “i
s
”. The relationship between bias current i
b
and signal current i
s
in first current signal i
1
218
can be expressed as shown in Eq. (1):
i
l
=i
b
+(1/2)(
i
s
),  Eq. (1)
while the

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