High speed, low-power CMOS circuit with constant output...

Details High speed, low-power CMOS circuit with constant output... High speed, low-power CMOS circuit with constant output...

2001-04-06

2002-12-31

Wambach, Margaret R. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S065000, C327S266000, C327S280000, C327S274000, C327S309000, C327S318000, C327S327000

Reexamination Certificate

active

06501317

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to delay circuits for use in a ring oscillator of a phase locked loop.
2. Background
Phase-Locked loops (PLL) are used in a number of applications, including communications, digital circuits and mass storage electronics. A number of designs for PLLs are known to a person of ordinary skill in the art. The conventional PLL designs include a voltage or current controlled oscillator (VCO or ICO), a critical part in determining the performance of the PLL. Important parameters of a VCO or ICO for a PLL include: (1) Tuning range, or the range between the minimum and maximum values of the VCO frequency with minimal variation of the output amplitude and low jitter; (2) Supply and substrate noise rejection; and (3) Power consumption.
FIG. 1
shows a conventional delay circuit which can be used in a ring oscillator of a VCO or ICO of a PLL. The delay circuit of
FIG. 1
is disclosed in IEEE JSSC, Vol. 31, No. 11, November 1996, pp. 1723-1732. Transistors
1
-
7
form a delay stage and transistors
11
and
12
provide the biasing for the delay circuit.
The delay stage contains a source-coupled pair of transistors
2
and
3
with resistive loads
4
-
7
. The loads each include a diode-connected PMOS device
4
or
5
in shunt with an equally sized biased PMOS device
6
or
7
. Transistors
4
-
7
are PMOS devices as illustrated by the circle provided on their gate, while transistors such as
2
and
3
without such a gate circle are NMOS devices. The gate circles are used to show which transistors are PMOS and NMOS devices in
FIG. 1
, as well as in subsequent figures.
For proper bias, the sizes of transistors
11
,
12
,
6
and
7
are chosen so that when, for example transistor
2
is fully on, transistor
6
draws ½ the current of transistor
1
. Likewise, if transistor
3
is fully on, then transistor
7
draws ½ the current of transistor
1
.
The delay circuit of
FIG. 1
has an output voltage swing from V
DD
to V
DD
−V
GS
. Here, V
GS
is a gate-source voltage equal to V
T
+2*I
D
/k, where k is the device transconductance of one of conducting load transistors
4
or
5
. I
D
is the drain current of one of transistors
4
or
5
, which is typically half of the tail current through transistor
1
, as controlled by the time delay control voltage V
CTL
.
The delay time of the delay circuit of
FIG. 1
can be approximated as T
D
=R
EFF
*C
EFF
=(1/2*k*I
D
)*C
EFF
. R
EFF
is the small signal resistance at the ends of the voltage swing ranges that is the inverse of the transconductance for one of the two conducting load transistors
4
or
5
. C
EFF
is the total effective capacitance and includes the drain capacitance of transistors
2
and
6
, the gate and drain capacitance of transistor
4
, and the gate capacitance of the input transistor of a next subsequent delay stage of the ring oscillator. Limiting the effective capacitance, C
EFF
, reduces power consumption and further can enable increased operation speed.
For a ring oscillator with N stages of the circuit shown in
FIG. 1
, the operating frequency f
1
of the ring oscillator will be:
f
1=1/(2
*N*T
D
)=2
*k*I
D
/(2
*N*C
EFF
)
Accordingly, the ring oscillator using the circuit shown in
FIG. 1
has the output voltage swing changing with I
D
and an operating frequency f
1
proportional to I
D
. Variations of the output voltage swing with I
D
is an undesirable feature because such variation decreases power supply and substrate noise rejection over the whole operating frequency range. Further, the tuning range of the operating frequency f
1
is controlled by limitations on the tail current I
D
according to the square root function.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved delay circuit for a VCO or ICO with a constant output swing, a wide tuning range, a high operation speed and low power consumption relative to the circuit of
FIG. 1
is provided.
In accordance with the present invention, referring to
FIG. 2
, a delay circuit is provided which may be used in a ring oscillator of a VCO or ICO. The delay circuit includes a differential pair of NMOS transistors
102
and
103
with an NMOS transistor
101
providing the tail current for the differential pair. Complementary NMOS and PMOS load transistors
104
,
106
and
105
,
107
provide loads for the differential transistors
102
and
103
. Transistors
111
-
114
and
121
-
122
together with an amplifier
130
provide biasing for the delay adjustment circuitry.
The amplifier
130
has a non-inverting (+) input set to V
DD
−V
CLAMP
, and W/L ratios of the transistors of the delay circuit are set so that either transistors
101
,
102
,
104
and
106
, or
101
,
103
,
105
and
107
replicate the biasing transistors
111
,
112
,
113
and
114
respectively. As configured, a constant output voltage swing from V
DD
to V
DD
−V
CLAMP
is provided at the outputs V
OUT
+ and V
OUT
− of the delay device. Since V
CLAMP
is independent of the control voltage V
CTL
which controls the bias tail current from transistor
101
, the output voltage swing of the time delay circuit will be constant for different tail currents as controlled by V
CTL
. The constant output voltage swing enables the delay circuit to provide better noise rejection relative to the circuit of
FIG. 1
over variations of operating current.
For the circuit of
FIG. 2
, the NMOS load transistors
104
or
105
contribute less to the effective capacitance C
EFF
which affects the operating frequency of a ring oscillator, whereas the PMOS transistors
4
or
5
of
FIG. 1
do, so the circuit of
FIG. 2
can obtain a higher operation speed without consuming more supply current. In addition, the frequency tuning range of a ring oscillator using the circuit of
FIG. 2
can be made wider than that of the circuit of
FIG. 1
because the operating frequency for a ring oscillator using the circuit of
FIG. 2
is proportional to the tail current whereas the operating frequency using the device of
FIG. 1
is proportional to the square root of the tail current.


REFERENCES:
patent: 5994939 (1999-11-01), Johnson et al.
patent: 6052003 (2000-04-01), Molin et al.
patent: 6304150 (2001-10-01), Shenoy
John G. Maneatis, Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques, IEEE Journal of Solid State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.

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