High speed low power cell providing serial differential signals

Coded data generation or conversion – Digital code to digital code converters – Parallel to serial

Reexamination Certificate

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Details

C341S100000, C341S141000, C326S038000, C326S115000, C327S108000, C327S144000, C327S407000

Reexamination Certificate

active

07990296

ABSTRACT:
Techniques are provided to serialize and delay parallel input data signals and are particularly useful for low power applications. In one example, a device includes a plurality of data input ports adapted to receive N parallel single-ended input data signals, and a clock input port adapted to receive a clock signal substantially synchronized with the parallel single-ended input data signals. The device also includes a cell adapted to serialize the parallel single-ended input data signals to provide N/2 first serial differential output data signals in response to the clock signal, delay the parallel single-ended input data signals, and serialize the delayed parallel single-ended input data signals to provide N/2 delayed second serial differential output data signals in response to the clock signal. The delayed second serial differential output data signals are delayed relative to the first serial differential output data signals. The device also includes a plurality of output ports.

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