High-speed, low power auto-zeroed sampling circuit

Details High-speed, low power auto-zeroed sampling circuit High-speed, low power auto-zeroed sampling circuit

1991-10-16

1993-11-16

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307355, 307362, 307491, H03K 524, G11C 2702

Patent

active

052626857

ABSTRACT:
Auto-zeroing clocking signals, a first auto-zeroing clocking signal of comparatively-low frequency and duty cycle and a second auto-zeroing clocking signal of the same comparatively-low frequency but complementary and comparatively-high duty cycle, and a sampling clocking signal of comparatively-high frequency respectively initiate auto-zeroing of a circuit element subject to output offset error and data sampling of an A.C. input signal to a latch. The sampling of the A.C. input signal to the latch occurs at the comparatively-high frequency of the clocking signal during the "on" time of the comparatively-high duty cycle second auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide higher speed sampling than heretofore possible. The auto-zeroing of the circuit element subject to input offset error occurs during the "on" time of the comparatively-low duty cycle first auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide lower power sampling than heretofore possible. Typically, the circuit element is either an analog comparator or an operational amplifier, and the sampling circuit of the invention has exemplary utility in analog-to-digital (A/D) conversion.

REFERENCES:
patent: 4316105 (1982-02-01), Fowler
patent: 4553052 (1985-11-01), Takahashi
patent: 4827161 (1989-05-01), Kunitoki et al.
Brooktree data sheet Bt251, entitled "15 MSPS Monolithic CMOS Single Channel 8-Bit Image Digitizer", Brooktree Corporation, 9950 Barnes Canyon Road, San Diego, Calif. 92121 consisting of pp. 1-20, 1989.

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