High speed, low gate/drain capacitance DMOS device

Details High speed, low gate/drain capacitance DMOS device High speed, low gate/drain capacitance DMOS device

1992-09-11

1993-12-28

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437150, 437157, 148DIG126, 257335, H01L 21336

Patent

active

052739228

ABSTRACT:
A DMOS device with field oxide formed in the channel between adjacent transistors and an impurity implanted through the same opening in which the field oxide is formed. The gate is deposited over the field oxide and spaced from the supporting epitaxial layer by the field oxide to reduce the gate-to-drain capacitance. The implanted impurity below the field oxide reduces ON resistance of the device.

REFERENCES:
patent: 3821776 (1972-06-01), Hayashi et al.
patent: 4810664 (1989-03-01), Kamins et al.
patent: 4987093 (1991-01-01), Teng et al.
patent: 5047820 (1991-09-01), Garnett
patent: 5121176 (1992-06-01), Quigg
patent: 5158901 (1992-10-01), Kosa et al.

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