High-speed low-distortion analog-to digital converter

Details High-speed low-distortion analog-to digital converter High-speed low-distortion analog-to digital converter

2003-08-22

2004-12-14

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S158000

Reexamination Certificate

active

06831584

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
Applications such as disk drive read channels, fiber optical receivers, front end and data communication links using multi-level signaling (e.g. PAM and QAM) require high speed analog-to-digital converters (ADCs). It is of particular interest that such ADCs be fabricated in a standard CMOS technology. The main challenges in ADC performance are as follows: static and dynamic offset, low supply operation, design trade-offs between power, speed and chip area, time interleaving, gain-bandwidth optimization, high-speed input signal feed through and interpolation.
FIG. 1
shows a generic, conventional analog-to-digital converter. As shown in
FIG. 1
, the conventional analog-to-digital converter includes a resistor ladder
104
comprised of equal resistors R, an amplifier array
101
, a corresponding array of latches
102
, and a decode circuit
103
.
The transistor performance in 0.18 &mgr;m CMOS process is ruled by threshold mismatch. Averaging, proposed by Kattman and Barrow, see “A Technique for Reducing Differential Nonlinearity Errors in Flash A/D Converters,”
ISSCC Digest of Technical Papers
, pp. 170-171, February. 1991, is a proven technique to reduce offsets of the amplifiers array. See also K. Bult, A. Buchwald et al., “A 170 mW 10b 50 MSample/s CMOS ADC in 1 mm
2
,” ISSCC Digest of Technical Papers
, pp. 136-137, February. 1997; H. Pan, et al., “A 12b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz,”
ISSCC Digest of Technical Papers
, pp. 38-39, February. 2000; M. Choi, A. A. Abidi, “A 6b 1.3 GSample/s A/D Converter in 0.35 &mgr;m CMOS,”
ISSCC Digest of Technical Papers
, pp. 126-127, February. 2001; and P. Scholtens and M. Vertregt, “A 6b 1.6 GSamples/s ADC in 0.18 &mgr;m CMOS Using Averaging Termination,”
ISSCC Digest of Technical Papers
, pp. 168-169, February. 2002, which are incorporated by reference herein. However, an effective method to fix the boundary bending caused by offset averaging needs to be developed.
In general, there are two issues at the boundaries of the averaging network. First, the zero crossing points drift from the input reference voltage level due to the symmetrical nature is destroyed at the boundaries. This cause systematic non-linearity error.
FIG. 2
illustrates zero-crossing shift versus amplifier position. Amplifier
101
A is a “left edge” amplifier (see top portion of
FIG. 2.
) the zero crossings at the edges shift from their ideal values, causing distortion and nonlinearity. However, as may be seen from the middle portion of
FIG. 2
, the zero crossings in the center of the array
101
are located at the “ideal” position.
Additionally, the bottom portion of
FIG. 2
shows another distorting edge effect, which is referred to as “offset distribution.” As may be seen from the figure, the closer to the edge of the array
101
one gets, the greater the offset distribution, resulting in additional nonlinearity.
Thus, the downstream averaging network collects fewer random components for averaging at the boundaries. This causes less differential nonlinearity/integral nonlinearity (DNL/INL) improvement. State-of-the-art ADCs either use a partial of the amplifier array as dummies to preserve the electrical behavior of an infinite array of amplifiers (see, e.g., K. Bult, A. Buchwald et al., supra and H. Pan, et al., supra), or use a termination method to suppress the zero-crossing shifts at the edge (see P. Scholtens and M. Vertregt, supra). The termination method can effectively restore the systematic error when R
0
<3R
1
, namely the averaging window is narrow and boundary issue is not serious. Yet the edges with termination have less averaging.
For the dummy approach (i.e., adding additional “dummy” amplifiers at the edges of array
101
), the wider the averaging window, the more dummies are needed. For example, M. Choi, A. A. Abidi, indicate that 18 dummies are needed for an averaging window covering 18 amplifiers. Furthermore, the more dummy amplifiers that are added to the array
101
, the greater the reduction in voltage headroom available for the analog-to-digital conversion, and the greater the power consumption of the ADC. For low voltage operation, this becomes unacceptable.
SUMMARY OF THE INVENTION
The present invention is directed to a high-speed analog-to-digital converter with low distortion that substantially obviates one or more of the problems and disadvantages of the related art.
There is provided an analog to digital converter including an array of differential input amplifiers. Each amplifier inputs an input voltage and a corresponding voltage reference, and outputs a differential signal representing a comparison of the input voltage and the corresponding voltage reference. A plurality of latches store the differential signal from each of the differential input amplifiers. A decoder converts the stored differential signals to N-bit digital output. A first interface amplifier is connected to a first edge amplifier of the array through a first cross point. A second interface amplifier is connected to a second edge amplifier of the array through a second cross point. The first interface amplifier and the second interface amplifier are connected to each other through a third cross point.
In another aspect there is provided an analog to digital converter including a reference ladder with a plurality of resistors and taps providing voltage references. At least one controllable current source in series with each tap adjusts the voltage reference of each tap. An array of differential input amplifiers, where each amplifier inputs an input voltage and a corresponding voltage reference, and outputs a differential signal representing a comparison of the input voltage and the corresponding voltage reference. A plurality of latches store the differential signal from each of the differential input amplifiers. A decoder converts the stored differential signals to N-bit digital output.
Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


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Singer, L. et al., “A 12b 65MSample/s CMOS ADC with 82dB SFDR at 120 Mhz”, ISSCC 2000, Session 2, Nyquist-Rate Data Converters, Paper MP 2.3, pp. 38-39, IEEE.
Kattman, K. et al., “A Technique for Reducing Differential Non-Linearity Errors in Flash A/D Converters”, ISSCC 91, Session 10, High-Speed Data Acquisition, Paper TP 10.4, pp. 170-171, IEEE.
Bult, K. et al., “A 170mW 10b 50Msample/s CMOS ADC in 1 mm2”,SSCC 97, Session 8, Data Converters, Paper FA 8.3; pp. 136-137, IEEE.
Geelen, G., “A 6b 1.1GSample/s CMOS A/D Converter”, ISSCC 2001, Session 8, Nyquist ADCs, Paper 8.2, pp 128-129, IEEE.
Choi, M. et al., “A 6b 1.3GSample/s A/D Converter in 0.35&mgr;m CMOS”, ISSCC 2001, Session 8, Nyquist ADCs, Paper 8.1, pp. 126-127, IEEE.
Scholtens, P. “A 6b 1.6GSample/s Flash ADC in 0.18&mgr;m CMOS using Averaging Termination”, ISSCC 2002, Session 10, High-Speed ADCs, Paper 10.2, pp. 68-69, IEEE.
International Search Report from PCT Appl. No. PCT/US03/27521, 5 pages, mailed Jan. 12, 2004.

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