High speed logic simulation system using time division emulation

Details High speed logic simulation system using time division emulation High speed logic simulation system using time division emulation

1993-09-13

1996-11-05

Teska, Kevin J.

Boots, shoes, and leggings

395920, 395921, 364488, 364491, 371 222, G06F 1700, G06F 9455

Patent

active

055727107

ABSTRACT:
A logic simulation system capable of handling a very large scale circuit while realizing a high speed simulation by retaining the parallelism of the simulation targets. The system includes: a host computer having data of the simulation target divided into a plurality of sections defining different simulation phases to be executed sequentially in time division; an emulator for emulating the simulation target, including: a plurality of programmable emulation chips for mapping the simulation target, each emulation chip having a memory with a plurality of memory banks provided in correspondence to the plurality of sections for registering mapping data specifying a function to be realized by each emulation chip in emulating each of the plurality of sections; a programmable network for interconnecting the plurality of emulation chips; and an emulation control unit for controlling the plurality of emulation chips and the network by sequentially switching the memory banks of the memory of each emulation chip and changing connections among the plurality of emulation chips provided by the network in emulating each of the plurality of sections; and an interface unit for interfacing the host computer and the emulator.

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Thaler et al.,"A data flow Technique for the Efficient Design of a Class of Parallel Non-Data Flow Signal Processors". IEEE 1990, pp. 2162-2173.

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