High speed logic circuits

Details High speed logic circuits High speed logic circuits

2003-04-04

2004-08-10

Tan, Vibol (Department: 2819)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S257000, C330S260000, C326S115000, C326S127000

Reexamination Certificate

active

06774721

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to electronic circuitry, and in particular to high-speed logic circuits and applications thereof.
BACKGROUND OF THE INVENTION
With recent advances in the electronic industry, logic circuits of increased speeds are required to process high speed signals, for example 10 Gigabit/second and ultimately 40 Gigabit/second serial bit streams arising in fiber optic transmission systems.
At the same time, the logical complexity of the circuits is constantly increasing in order to meet ever increasing complexity and numerous requirements of processing, for example of SONET and fast Ethernet protocols.
To meet these requirements, silicon circuits using smaller geometry are being developed. Smaller geometry technology, such as “0.18 micron technology” and below, provides the capability to design high density and complex CMOS circuits. The smaller geometry technology also provides a capability for higher speed circuitry.
Current Mode Logic (CML) circuitry has been developed by the industry to provide a high-speed logic circuit technology, which is compatible with CMOS circuitry, and allows the fabrication of both types of circuits in one device, or chip. Typically, the CMOS circuitry would provide the high-density complex logic processing part of the chip, while CML circuitry would be used in the high-speed serial interfaces that run at the serial bit rate and convert between the serial bit streams and the parallel bus signals processed by the CMOS circuitry. The speed of the serial interface may thus be many times higher than the speed of the CMOS circuitry.
In conventional synchronous logic design, a clock circuit drives the logic circuits including combinatorial logic functions (AND, OR, Mux, etc.) and storage elements (D-type flip-flops). In order to provide high-speed operation, it is necessary to control the current through each circuit to prevent saturation of the transistors (if bipolar technology is used) or triode region operation (if MOS technology is used).
A theoretical analysis of a basic CML circuitry can be found in the book “Analog Integrated Circuit Design” by David Johns and Ken Martin, published by John Wiley & Sons, 1997, pp. 142. An exemplary implementation of the CML circuitry, based on tail current sources (bias stage) and differential current steering through transistor pairs, as described, e.g. in the U.S. Pat. No. 6,424,194 to Hairapetian U.S. Pat. No. 6,424,194 entitled “Current-controlled CMOS logic family” issued Jul. 23, 2002, will be described with reference to
FIGS. 1A
to
1
C below.
FIG. 1A
shows one example of the prior art circuit arrangement
10
of a CML Logic Circuit
11
including a logic function circuit
12
coupled to a current source
14
, and a CML Clock Buffer
15
including a driver circuit
16
coupled to a current source
18
. The differential output
17
of the driver circuit
16
of the CML Clock Buffer
15
is coupled to a differential clock input
19
of the logic function circuit
12
of the CML Logic Circuit
11
. The input
13
of the driver circuit
16
of the CML Clock Buffer
15
is connected to a clock source (not shown). The differential output
19
a
of the logic function circuit
12
of the CML Logic Circuit
11
is connected to other logic circuits (not shown). The logic function circuit
12
may include other differential inputs (illustrated by a straight unmarked line extending from the logic function circuit
12
on its left) connected to the outputs of other logic function circuits
12
(not shown).
The current source
14
of the CML Logic Circuit
11
provides a bias current to the logic function circuit
12
, thus setting its operating point. Similarly, the current source
18
of the CML Clock Buffer
15
provides a bias current to the driver circuit
16
, thus setting its operating point.
FIGS. 1B and 1C
of the prior art show the details of the CML Logic Circuit
11
implemented in two technologies, namely the CML Logic Circuit
11
implemented by using a bipolar technology (CML Logic Circuit
20
) and by using MOS technology (CML Logic Circuit
30
) respectively. The detailed circuits
20
or
30
are representative of the combination of a typical logic function circuit
12
and current source
14
of the prior art.
The bipolar CML circuit
20
comprises transistors Q
30
, Q
31
n
, Q
31
p
, Q
32
n
, Q
32
p
, Q
33
n
, and Q
33
p
, as well as resistors R
30
, R
31
n
, and R
31
p
. The circuit is connected to power supply terminals Vcc, Vee, and a bias supply Vbias.
Differential data inputs in_n and in_p of the circuit are connected to an input data source (not shown), differential clock inputs ck_n and ck_p of the circuit are connected to a clock buffer (not shown), and differential data outputs out_n and out_p of the circuit are connected to a subsequent logic circuits (not shown). Differential inputs and outputs are pairs of terminals designated with the subscripts_n (negative) and_p (positive).
The power supply terminal Vcc is connected to a first lead
21
of the resistor R
31
n
and a first lead
22
of the resistor R
31
p
. Second leads of the resistors R
31
n
and R
31
p
(
23
and
24
) are respectively connected to the differential data outputs out_n and out_p. Also connected to the negative data output terminal out_n are the collectors of the transistors Q
32
n
and Q
32
p
as well as the base of the transistor Q
33
p
. Further connected to the positive data output terminal out_p are the collectors of the transistors Q
33
n
and Q
33
p
as well as the base of the transistor Q
32
p
. The differential data inputs in_n and in_p are connected to the bases of the transistors Q
33
n
and Q
32
n
respectively. The emitters of the transistors Q
33
n
and Q
32
n
are tied together and connected to the collector of the transistor Q
31
n
. The emitters of the transistors Q
33
p
and Q
32
p
are tied together and connected to the collector of the transistor Q
31
p
. The differential clock inputs ck_n and ck_p are connected to the bases of the transistors Q
31
n
and Q
31
p
respectively. The emitters of the transistors Q
31
n
and Q
31
p
are tied together and connected to the collector of the transistor Q
30
. The base of the transistor Q
30
is connected to the bias supply Vbias, and the emitter of the transistor Q
30
is connected to a first lead
25
of the resistor R
30
. A second lead of the resistor R
30
(
26
) is connected to the power supply terminal Vee.
Transistors Q
31
n
, Q
31
p
, Q
32
n
, Q
32
p
, Q
33
n
, and Q
33
p
and resistors R
31
n
and R
31
p
form a conventional latch circuit, providing a latch function: the value of the signal at the differential inputs in_n and in_p are transferred to the differential outputs out_n and out_p upon activation of the differential clock inputs ck_n and ck_p. Upon de-activation of the differential clock inputs ck_n and ck_p, the latch retains the output value due to the cross-coupling between the outputs out_p and out_n, and the bases of the transistors Q
32
p
and Q
33
p
respectively.
The current source
14
of the bipolar CML circuit
20
includes the transistor Q
30
, the resistor R
30
, and the bias supply Vbias, to supply the bias current to the latch circuit (the logic function circuit
12
).
In the CML circuits
20
of the prior art, the current source supplies a fixed current to the latch circuit, regardless of the operational state of the latch. This current flows through one of resistors R
31
n
or R
31
p
; through only one of the transistors Q
32
n
, Q
32
p
, Q
33
n
, Q
33
p
; and through one of the transistors Q
31
n
and Q
31
p
, depending on the state of the differential inputs in_n and in_p, and the differential clock inputs ck_n and ck_p.
The bias current is set, by the combination of the value of the bias supply Vbias and the resistor R
30
, to ensure that the voltage drop across resistors R
31
n
or R
31
p
(depending on the operational state of the latch) is high enough as a logic signal (voltage swing) at the circuit outputs out_n and out_p, but is not so high as to saturate the transistors.
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