High speed logic circuit

Details High speed logic circuit High speed logic circuit

1992-09-09

1994-03-08

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

257195, 257197, H03K 1908, H01L 29161

Patent

active

052930840

ABSTRACT:
In a high speed logic circuit using a vertical hetero-junction bipolar transistor, in which two-dimensional carriers formed at a semiconductor hetero-junction interface are used as a base layer, the uppermost layer being a collector layer, the lowest layer being an emitter layer, two base electrodes making contact with the base layer are disposed so as to put a collector electrode, which is electrically in contact with the collector layer, therebetween. The base electrodes are used at the same time as a source electrode and a drain electrode, respectively, of a field effect transistor using the two-dimensional carriers as an active layer. The high speed logic circuit is so constructed that one of the base electrodes of the bipolar transistor is an input terminal; the other is connected with a power supply; the emitter is grounded; and the collector is an output terminal.

REFERENCES:
patent: 4779014 (1988-10-01), Masuoka et al.
patent: 4821090 (1989-04-01), Yokoyama
patent: 5012318 (1991-04-01), Honjo
patent: 5151618 (1992-09-01), Yokoyama
patent: 5206546 (1993-04-01), Usami
IEEE Journal of Solid State Circuits, vol. SC-14, #3, Jun. 1979, pp. 585-590.
IEEE Transactions on Electron Devices, vol. 38, #2, Feb. 1991, pp. 222-231.
IEEE Journal of Solid-State Circuits, vol. SC-7, Oct. 1972, pp. 340-346.
IEEE Journal of Solid-State Circuits, vol. SC-7, Oct. 1972, pp. 346-351.

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