High speed linear variable gain amplifier architecture

Details High speed linear variable gain amplifier architecture High speed linear variable gain amplifier architecture

2001-12-10

2004-04-27

Mottola, Steven J. (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S259000, C330S283000

Reexamination Certificate

active

06727755

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to amplifiers and in particular, amplifiers having variable gain, large bandwidth and low distortion.
BACKGROUND OF THE INVENTION
Amplifiers are used to manipulate various signals within a circuit. The topology of the amplifier affects various operating aspects of the operating amplifier. For example, some amplifiers can deliver a high output current to a load. Other amplifiers can produce an output voltage swing that is approximately equal to the magnitude of the power supply of the amplifier circuit. Some amplifiers must provide an output with low cross-over distortion whereas other amplifiers are required to maintain gain and stability at high frequencies. These different requirements place constraints upon the design of the amplifier. It is often desirable in an amplifier circuit to have variable gain, large bandwidth and low distortion. Conventional solutions use attenuators as front ends followed by high gain, closed-loop amplifiers or multiple lower gain closed-loop amplifiers. Disadvantageously, these conventional solutions require much higher FT (factor of ten) amplification to achieve these results.
SUMMARY OF THE INVENTION
The present invention achieves technical advantages as a variable gain amplifier with wide bandwidth and low distortion by using two stages, a quad input stage with emitter degeneration and translinear current amplifier second stage.
The first stage quad configuration allows a constant DC output level. The output current of the quad is then fed into a resistance shunt current feedback amplifier with Darlington/level shift input stage to reduce transistor beta loading effects as well as allowing the largest dynamics out of the stage when a current to voltage and common mode feedback circuit are implemented in the same stage.
The second stage presents a low input impedance to the quad allowing optimization of the quad with minimize loss of bandwidth.


REFERENCES:
patent: 5901350 (1999-05-01), Stoichita et al.
patent: 5907261 (1999-05-01), Jones

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