High-speed leaf splitter for clock gating

Details High-speed leaf splitter for clock gating High-speed leaf splitter for clock gating

2001-09-06

2002-09-10

NuTon, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S176000

Reexamination Certificate

active

06448835

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to clocked microelectronic circuits, and in particular to a method and system for synchronously gating clock distribution trees. Still more particularly, the present invention relates to a system and method for providing two separately gated true and complementary clock signals at clock distribution tree leaves.
2. Description of the Related Art
The clock distribution system within a digital electronic system is typically organized as a tree structure as depicted in FIG.
2
. The tree structure depicted therein shows a clock repowering tree
215
and a clock gate repowering tree
210
in accordance with the prior art. A unique clock source, OSC, is the root of the tree. Every node of the tree branches to a fixed number of successor nodes. This number is called the branching factor. Every node of the clock distribution tree depicted in
FIG. 2
either has a non-zero number of successor nodes (i.e., an internal node), or does not have any successors at all (i.e., an external node). In the latter case, the node is a leaf of the tree.
In the clock tree distribution structure depicted in
FIG. 2
, the leaf nodes are shift register latches including SRL
212
and SRL
214
. SRLs comprise concatenated L1-L2 latch pairs having a design and functionality well known to those skilled in the art. SRLs
212
and
214
each require a dual, 180 degrees out-of-phase clock input for its L1/L2 latch pair. In the depicted example, clock splitters
206
and
208
provide such complementary clock signals for SRLs
212
and
214
, respectively.
The tree distribution structure illustrated in
FIG. 2
, provides clock signals to registers and follows a set of design rules different from those of any other network in a design. For most designs, this network must be constructed such that the clocking signals arrive at each register at roughly the same time, that is to say, with minimum skew. This is typically accomplished by building clock repowering tree
215
such that it has an equal number of levels between the source clock OSC and all it sinks. In addition, the loading of each cell of a given level of each repowering structure should be equal to the loading of all other cells at the same level. The aim of such design strategy is to ensure that the paths through the repowering structures are subject to the same amount of delay from clock source to sink, resulting in minimum skew of the arrival time of clocking signals from register to register.
Clock gate repowering tree
210
provides a balanced power up and power down capability for clock gating circuits. As illustrated in
FIG. 2
, clock gate repowering tree
210
includes a clock splitter
202
that converts a timing signal from OSC into a complementary pair of timing signals for the L1/L2 latch pair within a shift register latch (SRL)
204
. The gate signals provided by the clock gating circuits are utilized to selectably enable and disable the BCLK and CCLK clock signals at the outputs of clock splitters
206
and
208
. To this end, a BCLKGT signal and a CCLKGT signal are generated within SRL
204
in accordance with a data input signal into SRL
204
. The data signal into SRL
204
ideally provides synchronous control of the power up and power down of the circuitry supported by clock repowering tree
215
and clock gate repowering tree
210
.
Referring to
FIG. 1
, there is illustrated a conventional gated clock splitter circuit such as maybe implemented as clock splitter
206
or clock splitter
208
. The clock splitter circuit depicted in
FIG. 1
includes source timing input, OSC, and the gate signals BCLKGT and CCLKGT delivered from SRL
204
. BCLKGT and CCLKGT control gate the BCLK and CCLK splitter outputs, respectively, which are delivered as the final latch control signals for the L1/L2 latch pairs within SRLs
212
and
214
. The clock splitter circuit further includes an inverter
106
and a delay element
108
from which complementary gated output CCLK is generated in conjunction with gate signal CCLKGT. Gated timing signals BCLK and CCLK are formed to satisfy the timing requirements of functional on-chip SRLs at the leaves of the clock distribution tree depicted in FIG.
2
. Controlling or gating timing signals BCLK and CCLK is the typical method used to synchronously start and stop the functional on-chip SRLs such as SRLs
212
and
214
.
As illustrated in
FIG. 2
, the root for both clock repowering tree
215
and clock gate repowering tree
210
is system clock input OSC. The clock or timing signal provided at system clock input OSC is a single-phase clock signal that is distributed from a chip central clock buffer (not depicted) to all latches inside the macros in which clock repowering tree
215
and clock gate repowering tree
210
are distributed. The clock signal provided by OSC passes through clock repowering tree
215
until it reaches the leaf nodes including leaf node SRLs
212
and
214
via multiple clock splitters including clock splitters
206
and
208
.
Enabling the circuitry supported by clock repowering tree
215
to start and stop the latches in a particular sequence facilitates debugging of logic functions in the lab and self-testing the logic at functional speed to test for AC (performance) defects. To this end, it is important that the SRLs at the leaves of the clock distribution tree are started and stopped synchronously. The gated clock splitter/distribution designs illustrated in
FIGS. 1 and 2
have an inherently limited high-frequency performance due to a lack of clock distribution tracking and half-cycle gating paths. Referring to
FIG. 2
, a half-cycle path begins at the output of SRL
204
and ends at the BCLKGT and CCLKGT inputs into splitters
206
and
208
. The timing signal input into splitter
202
and SRL
204
does not track its counterpart at the inputs of splitters
206
and
208
well enough for higher frequency operation.
FIG. 3
depicts a timing diagram illustrating the operation of a gated clock splitter circuit such as gated clock splitter
206
or
208
. To ensure synchronous switching, the BCLKGT and CCLKGT signals generated by clock splitter
202
and SRL
204
must arrive at splitters
206
and
208
within a half-cycle so that all of the latches supported by clock repowering tree
215
and clock gate repowering tree
210
start on the same clock cycle and are not chopped or slivered (depending on whether the latches are gated on or off). The sheer number of levels and branches within the clock distribution tree result in the half-cycle timing requirement that becomes problematic for high-frequency operations.
It can therefore be appreciated that a need exists for an improved high-speed gated clock splitter for use in clock distribution and repowering trees. The present invention addresses such a need.
SUMMARY OF THE INVENTION
An apparatus and method for providing a gated output timing signal within a gated clock distribution tree are disclosed herein. In accordance with the present invention, a gated clock splitter includes a timing signal input and a combinatorial logic block coupled to the timing signal input that generates a gated timing signal. A gating signal input is coupled to the combinatorial logic block for selectively enabling and disabling the output from the combinatorial logic block. A gate control circuit is coupled to the gating signal input for providing a gate signal to the combinatorial logic block, wherein the gate control circuit provides a fall-cycle path for the gate signal to said gating signal input.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 5852378 (1998-12-01), Keeth
patent: 5867453 (1999-02-01), Wang et al.
patent: 5923613 (1999-07-01), Tien et al.
patent: 5949266 (1999-09-01), Hinds et al.
patent: 5977809 (1999-11-01), Wang et al.

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