High-speed leaf clock frequency-divider/splitter

Details High-speed leaf clock frequency-divider/splitter High-speed leaf clock frequency-divider/splitter

2011-03-29

2011-03-29

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S113000

Reexamination Certificate

active

07915929

ABSTRACT:
A novel clock splitter that has a local internal clock frequency-divider is presented. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses in the C clock to generate a slower C clock signal that is slower than the oscillator clock; and a B/C clock order logic, wherein the B/C clock order logic phase shifts the C clock relative to a B clock. The clock frequency-divider may selectively suppress pulses in the B clock to generate a slower B clock signal. The slower B and C clock signals may have a same or different frequency. In one embodiment, the clock splitter is located at a terminal leaf of a clock tree.

REFERENCES:
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patent: 2008/0169848 (2008-07-01), Douskey et al.
Office Action dated Dec. 19, 2008, U.S. Appl. No. 11/859,175, USPTO.

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