Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2001-02-23
2004-05-18
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S212000
Reexamination Certificate
active
06737899
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to circuits. More particularly, it relates to a high-speed latch with integrated gate, which has improved switching performance and may be used in various applications such as a prescaler for a frequency synthesizer.
Latches and gates are commonly used to implement various logic functions. For example, latches may be used to implement flip-flops, which may then be used with gates to implement a dual modulus divider capable of dividing an oscillator signal by one of two (or possibly more) divide factors. An example design of such dual modulus divider is described below. For some applications (e.g., wireless, networking, and so on), the oscillator signal may be a radio frequency (RF) signal. The dual modulus divider is typically the fast operating logic on a device, and may be required to operate based on the RF signal. In this case, if the dual modulus divider can be designed to operate faster, a higher oscillator frequency may be supported and new applications may be possible.
To increase the operating speed of the dual modulus divider, it is necessary to reduce the propagation delay between flip-flops. If a gate is inserted between stages of the flip-flop, additional delay is introduced which then limits the speed at which the flip-flops may be triggered. To reduce the propagation delay, the gate may be integrated within the appropriate flip-flop. However, as described in further detail below, the integration of the gate within the flip-flop typically results in an input stage that is a single-ended design (as oppose to a differential design) having degraded switching performance.
As can be seen, a high-speed latch having an integrated gate and improved switching performance is highly desirable. This latch with integrated gate may be advantageous used for various high-speed logic circuits, such as a prescaler, required to operate at a high clock frequency.
SUMMARY OF THE INVENTION
The invention provides techniques to improve the operating speed and switching performance of a latch having an integrated gate. Via the use of a (positive) feedback circuit, various improvements in performance may be obtained such as (1) faster signal swing on the output signal, (2) stronger output signal drive, (3) improved noise margin, and so on. The feedback circuit may be used to implement high-speed logic based on, for example, current-mode logic (CML). The improvements provided by the feedback circuit are especially advantageous for logic circuit implemented in complementary metal oxide semiconductor (CMOS), which is inherently a slower process than some other processes such as bipolar and bipolar-CMOS.
An embodiment of the invention provides a latch that includes first and second differential amplifiers and a feedback circuit. The first differential amplifier has a number of first (e.g., non-inverting) inputs and a second (e.g., inverting) input, receives and senses the input signals applied to the non-inverting inputs during a “sensing” phase of the latch, and provides a differential output. The non-inverting inputs may correspond to the gates of a number of transistors coupled in parallel to form, e.g., an OR function. The second differential amplifier latches the differential output during a “latching” phase of the latch. The feedback circuit detects the (e.g., non-inverting node of the) differential output and provides a control signal for the inverting input of the first differential amplifier. The latch typically further includes a fourth differential amplifier that receives a differential clock signal, activates the first differential amplifier during the sensing phase, and activates the second differential amplifier during the latching phase.
The feedback circuit can provide positive feedback between the output of the latch and the inverting input of the first differential amplifier. This feedback can provide various improvements in the output signal characteristics. For example, the control signal can dynamically adjust the inverting input of the first differential amplifier to provide improved switching performance. This dynamic adjustment can be achieved by driving the inverting input to a polarity that is opposite from a voltage generated by the OR of the input signals applied to the non-inverting inputs.
The feedback circuit can be implemented with a third differential amplifier comprised of a pair of transistors having sources that couple together. One transistor has a gate that couples to the inverting output of the latch and a drain that couples to the inverting input of the first differential amplifier. The other transistor has a gate that can couple to a bias voltage, V
B
, or to the non-inverting output of the latch, and a drain that can couple to a resistive or active load or the supply voltage, V
CC
.
Another embodiment of the invention provides a dual modulus divider (which may be used for a prescaler in a frequency synthesizer). The dual modulus divider includes a number of flip-flops coupled in series. Each flip-flop receives one or more input signals at a data input, registers the one or more input signals with a clock signal received at a clock input, and provides an output signal. At least one flip-flop includes an integrated gate at its data input. Each flip-flop with an integrated gate includes a feedback circuit configured to provide a control signal that improves the switching performance of the flip-flop. For example, the flip-flop may include a latch that may be designed in the manner described above. The dual modulus divider may include, for example, three flip-flops and may be configurable to divide the input clock signal by one of a number of divider ratios (e.g., 4 and 5).
Various other aspects, embodiments, and features of the invention are also provided, as described in further detail below.
REFERENCES:
patent: 4276488 (1981-06-01), Benedict et al.
patent: 5563533 (1996-10-01), Cave et al.
patent: 5796273 (1998-08-01), Jung et al.
patent: 5892382 (1999-04-01), Ueda et al.
patent: 5903175 (1999-05-01), Miyashita
patent: 6107853 (2000-08-01), Nikolic et al.
Dinh & Associates
Resonext Communications, Inc.
Tran Toan
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